Binary Tanner Graph Decoding for Non-Binary LDPC in SSDs
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Solution Overview
Problem
Non-binary LDPC codes face high complexity and performance losses in SSD devices due to the complexity of Q-ary sum-product algorithms and error-floor issues with low column weight codes, limiting their practical application in SSD devices.
Innovation Solution
A method for iteratively decoding read bits encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2r) is implemented, using a binary Tanner graph expansion based on a Q-ary Tanner graph, with binary variable nodes and check nodes, and iteratively updating bit reliabilities through Belief Propagation algorithms to improve decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-binary LDPC codes are used in SSD devices, then error correction capability is improved, but decoding complexity increases due to Q-ary sum-product algorithm complexity
Solution Approach 1:
The patent segments the Q-ary LDPC decoding problem into multiple binary LDPC decoding stages. By transforming the Q-ary Tanner graph into an expanded binary Tanner graph where each Q-ary variable node is replaced by r binary variable nodes (where Q=2^r), the complex Q-ary sum-product algorithm is divided into simpler binary decoding operations that can be executed sequentially or in parallel, significantly reducing the overall decoding complexity while maintaining error correction capability.
Solution Approach 2:
The patent introduces binary coset representation as an intermediary mechanism to bridge Q-ary LDPC codes and binary decoding algorithms. Each element in the Galois field GF(Q) is represented by a binary vector of length r through coset decomposition, allowing the Q-ary code to be decoded using binary LDPC techniques. This intermediary representation enables the use of simpler binary algorithms while preserving the error correction properties of the original non-binary code.
2Measurement precision
If Q-ary sum-product algorithm is used for decoding, then decoding accuracy is improved, but computational complexity and processing time increase
Solution Approach 1:
The decoding process is segmented into multiple binary decoding iterations, each operating on a subset of the code structure. Instead of performing one complex Q-ary sum-product iteration, the patent executes multiple simpler binary decoding steps on the expanded binary Tanner graph, reducing the computational burden per iteration and allowing for more efficient parallel processing, thereby decreasing total processing time while maintaining accuracy.
Solution Approach 2:
The patent changes the fundamental parameter of the decoding algorithm by transforming the Q-ary code into an equivalent binary representation. This parameter change from Q-ary to binary domain allows the use of faster binary arithmetic operations and simpler logic circuits, significantly reducing processing time while the iterative nature of the binary decoding maintains the required decoding accuracy through multiple passes.
3Device complexity
If binary Tanner graph expansion is applied, then decoding complexity is reduced, but graph size and memory requirements increase
Solution Approach 1:
The expanded binary Tanner graph is processed in segmented stages rather than as a single monolithic structure. The patent divides the decoding into multiple binary LDPC steps, each handling a portion of the expanded graph, which allows memory to be reused across iterations and reduces the peak memory requirements despite the increased graph size. This segmentation enables manageable processing of the larger graph structure.
Solution Approach 2:
The patent employs a nested structure where the expanded binary Tanner graph is organized hierarchically, with groups of binary variable nodes nested within the structure of the original Q-ary code. This nesting allows efficient memory access patterns and enables the use of the same memory resources across different levels of the hierarchy, reducing overall memory requirements despite the expanded graph size.
Data Source
AI summary
A method for iteratively decoding read bits in a solid state storage device, wherein the read bits are encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2r) and having length N. The method comprises: determining a binary Tanner graph of the Q-ary LDPC code based on a binary coset representation of the Galois field GF(2r) the binary Tanner graph comprising (2r−1) binary variable nodes, (2r−1−r) binary parity-check nodes each one connected to one or more binary variable nodes according to the binary coset representation and (2r−1) binary check nodes each one connected to a respective binary variable node mapping the read bits into N symbols providing each symbol of the N symbols to a respective Q-ary variable node; providing each bit of the symbol to a respective binary variable node of the respective Q-ary variable node and iteratively decoding each symbol.