Binary Stochastic TDC Staging for Low-Spur Time Resolution
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Solution Overview
Problem
Time-to-digital converters (TDCs) face challenges in minimizing quantization error and achieving low in-band phase noise due to high peak-power consumption and spurious signals, particularly in systems requiring large dynamic range and fine resolution, such as wireless radio standards.
Innovation Solution
A binary stochastic time-to-digital converter is introduced, which uses a multistage approach with successive approximation to determine the time difference between signals by applying progressively smaller delays, reducing the number of sampling elements and power consumption while maintaining high dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large ensemble of sampling elements is used to achieve fine resolution and large dynamic range, then measurement precision is improved, but power consumption increases and spurious signals are generated
Solution Approach 1:
The TDC is divided into multiple stages, with each stage containing a subset of sampling elements. The sampling elements are distributed across stages rather than all operating simultaneously, allowing the large ensemble to be segmented into smaller groups that operate sequentially or in reduced numbers, thereby reducing peak power consumption while maintaining the ability to achieve fine resolution through the combined output of all stages.
2Measurement precision
If a large ensemble of sampling elements is used to achieve fine resolution and large dynamic range, then measurement precision is improved, but spurious signals are generated
Solution Approach 1:
By segmenting the sampling elements into multiple stages, the simultaneous switching activity that causes spurious signals is reduced. Each stage processes a portion of the measurement, and the segmented operation prevents the large ensemble from switching all elements at once, thereby reducing the generation of spurious signals while still achieving the required quantization resolution through the combined measurement capability of all stages.
3Measurement precision
If a large ensemble of sampling elements is used to achieve fine resolution and large dynamic range, then measurement precision is improved, but chip area increases
Solution Approach 1:
The sampling elements are segmented into multiple stages and arranged in a distributed fashion across the chip. This segmentation allows for more efficient spatial utilization, where each stage can be compactly designed and the stages can be interconnected with minimal routing overhead. The segmented architecture enables the large ensemble required for fine resolution to be implemented with reduced total chip area compared to a monolithic single-stage design.
4Object-generated harmful factors
If current spikes from TDC sampling operation are masked to prevent supply voltage changes, then harmful factors are reduced, but device complexity increases
Solution Approach 1:
By segmenting the sampling operation into multiple stages, the current draw from each stage is reduced compared to activating all sampling elements simultaneously. This segmentation inherently reduces the magnitude of current spikes that require masking, thereby reducing the complexity of the masking circuits needed to prevent supply voltage variations. The segmented approach addresses the harmful effect at its source rather than requiring complex post-hoc masking.
Data Source
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AI summary
A method and apparatus for determining a difference between signal edges in two signals includes a multiple stage converter where each stage determines which of the two signals has an earlier signal edge, outputs a value corresponding to that determination, and then applies a delay to the earlier signal that is equal to half of the delay applied by the next previous stage. The stages examine smaller and smaller intervals to the sought-after signal edge. Each stage includes a plurality of logic elements. If all logic elements in the stage output the same signal, the edge position is clear. If some of the logic elements in the stage vote differently than others in the state due to differences in setup time for the different elements, the edge location has been found within the sensing band of the stage.