Binary to Ternary Converter for Multilevel Memory
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Solution Overview
Problem
Current memory technologies face challenges in efficiently utilizing ternary data storage, as direct conversion between binary and ternary data is lossless, leading to suboptimal memory cell utilization and increased production costs due to the need for additional states beyond binary bits.
Innovation Solution
A 3-to-2 converter is implemented to convert binary data to ternary data before writing to memory, allowing for efficient storage and retrieval, utilizing a conversion ratio that optimizes memory operations and reduces production costs by utilizing existing memory devices with minimal physical modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct conversion between binary and ternary data is used, then data integrity is maintained, but memory cell utilization is suboptimal and production costs increase
Solution Approach 1:
The patent applies parameter changes by implementing a 3-to-2 converter that transforms binary data into ternary data with an optimized conversion ratio. This changes the data representation parameter from binary (2 states) to ternary (3 states), allowing three binary bits to be converted into two ternary trits, thereby increasing memory cell utilization while maintaining data integrity through controlled conversion parameters
2Productivity
If additional states beyond binary bits are introduced, then memory capacity increases, but production costs increase
Solution Approach 1:
The patent applies universality by designing a converter system that can handle both binary-to-ternary conversion for writing and ternary-to-binary conversion for reading. This multi-functional converter uses existing memory device infrastructure with minimal physical modifications, allowing the same hardware to support both conversion directions and reducing manufacturing complexity despite introducing additional states
Data Source
AI summary
A memory device including a memory array comprising a plurality of memory cells, respective memory cells each comprising a storage element comprising phase change memory programmable to three unique states; and a controller comprising circuitry, the controller to convert binary data into ternary data at a ratio of three bits of binary data to two trits of ternary data and provide the ternary data to the memory array for storage.