Binary-Ternary LUT Mapping to Limit Error Propagation
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Solution Overview
Problem
Existing binary to ternary mapping schemes in multi-level flash memory suffer from error propagation, requiring complex hardware and resulting in a high bit error rate due to the conversion of ternary symbols to binary bits, which is inefficient and prone to errors.
Innovation Solution
A 19-12 mapping using look-up tables (LUTs) is implemented to efficiently convert binary data to ternary and back, reducing the complexity of hardware to approximately 100 gates, closer to the theoretical storage limit of 1.5849 bits per cell, and minimizing error propagation by using logic gates for binary to ternary and ternary to binary conversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If typical binary to ternary mapping is used, then storage density is improved, but bit error rate increases due to error propagation
Solution Approach 1:
The patent changes the mapping parameters by using a non-uniform mapping scheme where certain ternary symbols are assigned different weights. Specifically, it uses a mapping where 0 maps to 0, 1 maps to 1, 2 maps to 3, 3 maps to 2, and 4 maps to 1, creating an asymmetric distribution that reduces error propagation. This parameter change in the mapping function allows the system to achieve both high storage density and low bit error rate by optimizing how binary values are transformed to ternary symbols.
2Productivity
If complex mapping operations are used to achieve theoretical storage limit, then storage efficiency is improved, but hardware complexity increases
Solution Approach 1:
The patent segments the mapping operation into two independent lookup tables: one for binary-to-ternary mapping and another for ternary-to-binary mapping. Each LUT is pre-computed and stored in memory, allowing the complex mapping logic to be implemented through simple table lookups rather than complex computational circuits. This segmentation reduces hardware complexity while maintaining storage efficiency close to the theoretical limit of 1.585 bits per cell.
Solution Approach 2:
The patent applies preliminary action by pre-computing and storing the mapping relationships in lookup tables before runtime. The binary-to-ternary mapping table and ternary-to-binary mapping table are prepared in advance, containing all possible mapping relationships. During operation, the system only needs to perform table lookups based on the input values, which dramatically simplifies the hardware requirements compared to performing complex mapping calculations in real-time.
3Device complexity
If uniform binary to ternary mapping is used, then implementation is simplified, but error propagation increases by factor of 3.5
Solution Approach 1:
The patent applies asymmetry by using a non-uniform mapping scheme where different ternary symbols represent different numbers of binary bits. The mapping is asymmetric: 0→0, 1→1, 2→3, 3→2, 4→1, creating an uneven distribution that optimizes error performance. This asymmetric mapping reduces the error propagation factor from 3.5 in uniform mapping to a lower value, while the use of lookup tables keeps the implementation complexity manageable.
Data Source
AI summary
Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.