Binary Translated Code Integrity Validation
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Solution Overview
Problem
Current techniques for dynamically optimizing code in processors are inefficient and inadequate in protecting the integrity of original code in multi-core environments, leading to computational errors and inefficiencies.
Innovation Solution
The use of data structures such as IP-to-TCP tables, PPSTs, and XGCs to store and validate the integrity of optimized code, ensuring that only valid and unmodified code is executed by redirecting execution from original to translated code and monitoring physical memory locations for changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dynamic code optimization is implemented to increase performance, then execution speed is improved, but code integrity protection deteriorates in multi-core environments
Solution Approach 1:
The patent introduces an intermediary validation mechanism using translation lookaside buffers (TLBs) and translation invalidation buffers (TIBs) that mediate between the optimized code execution and the original code integrity. These buffers act as intermediaries to track and validate code translations, preventing execution of modified code while maintaining performance benefits.
Solution Approach 2:
The patent implements feedback mechanisms where the system continuously monitors code integrity through validation buffers that track modifications to original code. When code is detected as modified, the system receives feedback and invalidates the corresponding translated code, creating a closed-loop protection system that maintains reliability while enabling optimization.
2Productivity
If code optimization is performed to reduce instruction path length, then processing efficiency is improved, but the ability to protect original code integrity deteriorates
Solution Approach 1:
The patent segments the code execution into original code segments and translated optimized segments, tracking each segment's integrity separately. By dividing the code into manageable segments that can be independently validated and translated, the system maintains processing efficiency while enabling granular integrity protection through segment-specific validation buffers.
Solution Approach 2:
The patent creates copies of the original code in translation lookaside buffers (TLBs) that store validated translations. These copies serve as references to verify integrity - if the original code is modified, the copy in the TLB becomes invalid and is discarded. This copying mechanism allows efficient execution of optimized code while maintaining the ability to verify and protect original integrity.
3Speed
If dynamic code translation is used to optimize performance, then execution speed is improved, but the complexity of validating code integrity increases
Solution Approach 1:
The patent makes the validation buffers serve multiple functions: they track code translations, validate integrity, and manage cache coherence simultaneously. By making these structures multi-functional, the system reduces overall complexity - the same buffers used for performance optimization also handle integrity validation, eliminating the need for separate dedicated validation hardware.
Solution Approach 2:
The patent merges the code optimization and integrity validation functions into a unified system using combined buffers that handle both translation and validation operations. The translation invalidation buffers (TIBs) and translation lookaside buffers (TLBs) are merged with the optimization infrastructure, allowing the same hardware components to serve dual purposes and reducing overall system complexity.
Data Source
AI summary
The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.