Binary Translation Performance Scaling via Dynamic Power Adjustment

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Solution Overview

Problem

Binary translation of executable code from one instruction set architecture (ISA) to another often results in performance degradation, leading to noticeable speed differences in user experiences, particularly in interactive applications, due to architectural differences and the overhead of translation.

Innovation Solution

The solution involves dynamically adjusting the power-performance state of processing hardware to compensate for translation overhead by identifying translated code and adjusting parameters such as clock frequency, voltage, and core assignment, ensuring translated code executes faster than non-translated code.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If binary translation is used to enable cross-ISA execution, then code portability is improved, but execution performance deteriorates

Engineering Contradiction:

Improvecode portabilityVSAvoidexecution performance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The system dynamically changes hardware parameters (clock frequency, voltage, core assignment) based on whether code is translated or native, adjusting performance parameters to compensate for translation overhead and eliminate measurable performance differences between translated and native code execution

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If translated code executes at normal speed, then power consumption is reduced, but user experience deteriorates due to noticeable speed differences

Engineering Contradiction:

Improvepower consumptionVSAvoiduser experience

Core Design Contradiction:

Use of energy by moving objectVSEase of operation

Solution Approach 1:

The system uses feedback from identifying translated code to dynamically adjust power-performance state, creating a closed-loop control that monitors code translation status and responds by adjusting hardware parameters to maintain consistent user experience across both translated and native code

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

Hardware parameters such as clock frequency and voltage are dynamically changed based on the translation status of executing code, allowing the system to optimize between power consumption and performance based on real-time conditions

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12001844B2Performance scaling for binary translation

Publication Date: 2024.06.04 MICROSOFT TECHNOLOGY LICENSING LLC

AI summary

Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.