Binary Translator for Dynamic Hardware Accelerator Offload
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Solution Overview
Problem
Existing computing devices require manual rewriting of applications to target specific hardware accelerators, limiting the ability to dynamically optimize general-purpose code for performance and power efficiency across various hardware accelerators.
Innovation Solution
A computing device with a processor that includes a profiler to identify acceleration candidates, a binary translator to convert code for specific hardware accelerators, and a runtime offload framework to dynamically select and execute code on the most suitable hardware accelerator, enhancing performance and power efficiency without manual software modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If applications are manually rewritten to target specific hardware accelerators, then performance and power efficiency are improved, but development complexity and time increase
Solution Approach 1:
The patent introduces a binary translator as an intermediary component that automatically translates general-purpose code into hardware accelerator-specific code. This mediator handles the complexity of targeting specific accelerators, allowing developers to write code for general-purpose processors while the translator manages the conversion to optimized accelerator code, thus improving performance without increasing development complexity
Solution Approach 2:
The system implements self-service through automatic code translation and runtime offload decisions. The binary translator and runtime framework automatically identify suitable acceleration candidates and translate them without requiring developer intervention, enabling the system to optimize itself and eliminate manual rewriting requirements
2Ease of operation
If general-purpose code is executed without acceleration, then ease of operation is maintained, but performance and power efficiency deteriorate
Solution Approach 1:
The runtime framework automatically profiles applications to identify acceleration candidates and manages the offload process without requiring user or developer action. The system self-services by autonomously determining which code segments should be accelerated and handling the translation and execution on hardware accelerators, maintaining ease of operation while improving performance
Solution Approach 2:
The binary translator serves as an intermediary that operates transparently between the general-purpose code and hardware accelerators. It automatically translates and manages accelerated code execution without requiring changes to the original application or user interaction, thus preserving ease of operation while enabling performance improvements
3Use of energy by moving object
If code is translated to target specific hardware accelerators, then power efficiency is improved, but system complexity increases
Solution Approach 1:
The binary translator acts as an intermediary that handles the complexity of translating code for different hardware accelerators. It manages the translation process and runtime offload decisions, shielding the user and simplifying the system interface while enabling power-efficient execution on specialized hardware
Solution Approach 2:
The binary translator is designed with multi-functionality to support translation for multiple types of hardware accelerators. This universal approach allows a single translation framework to handle various accelerator types, reducing overall system complexity compared to having separate translation systems for each accelerator type
Data Source
AI summary
Technologies for dynamic acceleration of general-purpose code include a computing device having a general-purpose processor core and one or more hardware accelerators. The computing device identifies an acceleration candidate in an application that is targeted to the processor core. The acceleration candidate may be a long-running computation of the application. The computing device translates the acceleration candidate into a translated executable targeted to the hardware accelerator. The computing device determines whether to offload execution of the acceleration candidate and, if so, executes the translated executable with the hardware accelerator. The computing device may translate the acceleration candidate into multiple translated executables, each targeted to a different hardware accelerator. The computing device may select among the translated executables in response to determining to offload execution. The hardware accelerators may include, for example, a processor graphics, an image signal processor, or a field-programmable gate array. Other embodiments are described and claimed.