Binary Translator Eliminates Redundant Store Instructions

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Solution Overview

Problem

Modern processors face inefficiencies in executing complex instructions, such as floating-point operations and data moves, which slow down overall processing speed, especially in applications requiring simultaneous execution of multiple data items like multimedia and scientific tasks.

Innovation Solution

The implementation of Total Store Elimination (TSE) in an out-of-order processor, using a binary translator to optimize instruction streams by eliminating redundant stores and maintaining total store order, thereby enhancing execution efficiency and reducing redundant operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If out-of-order execution is employed to increase processing utility, then instruction execution speed is improved, but maintaining total store order becomes more complex

Engineering Contradiction:
Improveinstruction execution speedVSAvoidstore order maintenance complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates redundant store instructions from the execution stream before they reach the execution units. By identifying and removing stores that will not affect the final memory state, the system simplifies the store order maintenance problem while preserving out-of-order execution benefits, as fewer stores need to be tracked and ordered.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary analysis of store instructions to identify redundant ones before execution. The binary translator and runtime system detect redundant stores in advance and eliminate them, so that the execution core does not need to complexly manage store ordering - the redundant work is removed beforehand.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If redundant store instructions are eliminated, then execution efficiency is improved, but ensuring total store order becomes more difficult

Engineering Contradiction:
Improveexecution efficiencyVSAvoidtotal store order guarantee
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a binary translator and runtime system as intermediary components that analyze, identify, and eliminate redundant store instructions while preserving the necessary store order. This intermediary layer handles the complexity of redundancy detection and order maintenance, allowing the core execution system to achieve high efficiency without sacrificing reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs feedback mechanisms where the runtime system monitors execution and memory state to dynamically identify redundant stores. By continuously feedback on which stores are redundant based on subsequent loads and memory operations, the system efficiently eliminates unnecessary stores while maintaining correct store order for essential operations.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If complex instructions like floating-point operations are executed, then processing capability is improved, but execution speed decreases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidexecution speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent extracts and eliminates redundant complex instructions, particularly redundant floating-point operations and data move instructions, from the execution stream. By removing these unnecessary complex operations, the system maintains high processing capability for needed operations while improving overall execution speed by eliminating wasted complex instruction cycles.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10120686B2Eliminating redundant store instructions from execution while maintaining total store order
Publication Date: 2018.11.06 INTEL CORP
  • US10120686B2 patent drawing
  • US10120686B2 patent drawing
  • US10120686B2 patent drawing

AI summary

A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.