Binary-Weighted Multiplier-Accumulator for Faster Vector-Matrix Multiplication

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Solution Overview

Problem

Conventional vector-matrix multiplication operations require significant processing resources and energy, and are inefficient in terms of clock cycles and space due to their digital or hybrid analog implementations.

Innovation Solution

A method and apparatus for performing successive binary-weighted digital-to-analog conversion by sequentially performing vector-matrix multiplication operations for each bit-order of an input vector, converting analog outputs into digital bit values, and using a binary-weighted analog-to-digital converter to reduce the number of clock cycles and space requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional digital or hybrid analog componentry is used for vector-matrix multiplication, then the operation can be performed with standard processing components, but it consumes significant processing resources and energy while requiring a relatively large number of clock cycles and large area of space

Engineering Contradiction:

Improveoperation speedVSAvoidenergy consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent replaces conventional digital processing components with an analog vector-matrix multiplication circuit that performs calculations using analog electrical signals. The circuit uses operational amplifiers, resistors, and capacitors to implement the multiplication and accumulation operations in the analog domain, eliminating the need for traditional digital processors and significantly reducing energy consumption and operation time

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operational parameters by using continuous analog voltage or current signals instead of discrete digital values. The analog circuit operates with continuous parameters that can represent multiple bits simultaneously, allowing parallel processing of multiple data elements and achieving faster operation with lower energy consumption

Inventive Principle:

Principle #35Parameter changes

2Productivity

If conventional digital or hybrid analog componentry is used for vector-matrix multiplication, then the operation can be performed with standard processing components, but it requires a relatively large area of space to implement

Engineering Contradiction:

Improveoperation speedVSAvoidcircuit area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent merges multiple processing functions into a single integrated analog circuit. The vector-matrix multiplication circuit combines multiplication, accumulation, and result generation in one unified analog structure, eliminating the need for separate digital processors, memory units, and control logic that would occupy large areas in conventional implementations

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent replaces bulky digital processing components with compact analog circuit elements. Operational amplifiers and passive components implement complex mathematical operations in a space-efficient manner, reducing the overall circuit area while maintaining high operation speed

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If conventional analog componentry is used for vector-matrix multiplication, then the operation can be performed in parallel, but it requires a relatively large number of clock cycles to complete

Engineering Contradiction:

ImprovethroughputVSAvoidclock cycles

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent replaces sequential digital clock-cycled operations with continuous analog signal processing. The analog circuit performs multiplication and accumulation simultaneously using electrical signal interactions, eliminating the need for discrete clock cycles and achieving completion in a single operational phase rather than multiple sequential steps

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent maintains continuous analog signal flow throughout the computation process. Input signals are continuously processed through the analog circuit without interruption or discretization into clock cycles, allowing the useful computational action to proceed uninterrupted and complete faster than sequential digital operations

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11354383B2Successive bit-ordered binary-weighted multiplier-accumulator

Publication Date: 2022.06.07 APPLIED MATERIALS INC

AI summary

Various arrangements for performing successive vector-matrix multiplication may include sequentially performing a first vector-matrix multiplication operation for each bit-order of values in an input vector. The first vector-matrix multiplication operation for each bit-order may generate an analog output. For each analog output generated by the vector-matrix multiplication operation, an analog output may be converted into one or more digital bit values, and the one or more digital bit values may be sent to a second vector-matrix multiplication operation.