Binned Pixel Circuit Layout for Low-Leakage CMOS Imaging
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Solution Overview
Problem
Existing methods for CMOS image sensors fail to efficiently capture variable, adaptive gain as well as binning in charge mode in the focal plane, leading to increased leakage current and noise, especially in X-ray imaging applications where high sensitivity and wide dynamic range are required.
Innovation Solution
A novel CMOS active pixel design with a multi-pixel binned circuit that includes a lateral overflow circuit and a unique transistor arrangement to minimize leakage current and noise, allowing for variable gain and binning in charge mode, enhancing sensitivity and dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional binning methods are used in CMOS image sensors, then binning functionality is achieved, but leakage current and noise increase
Solution Approach 1:
The pixel array is divided into multiple independently controllable pixel units, each with its own binning transistor. This segmentation allows selective binning of adjacent pixels while maintaining low noise performance, as each pixel's charge can be independently transferred to a shared readout circuit without accumulating leakage from multiple transistors in series.
Solution Approach 2:
A floating diffusion region serves as an intermediary node between the photodiode and the readout amplifier. This floating diffusion acts as a charge summation point where charges from multiple pixels are combined before amplification, enabling binning functionality while isolating the leakage current path from the final output signal.
2Adaptability or versatility
If multiple transistors are added to achieve high dynamic range, then dynamic range is improved, but leakage current increases
Solution Approach 1:
The pixel circuit implements dynamic gain switching through a gain control transistor that can switch between high-gain and low-gain modes. In high-gain mode, the circuit operates with fewer active transistors to minimize leakage, while in low-gain mode, additional transistors are engaged to handle higher signal levels, thus adapting the transistor count to the signal requirements.
Solution Approach 2:
Different regions of the pixel circuit are designed with different transistor characteristics. The input photodiode region uses high-quality junctions with minimal leakage, while the output amplification region uses transistors optimized for gain. The binning transistor specifically uses a design that minimizes its leakage contribution to the signal path.
3Measurement precision
If integration time is extended to capture more signal, then signal detection capability is improved, but dark current noise increases
Solution Approach 1:
A reset transistor is used to perform preliminary action by clearing accumulated dark current charge from the floating diffusion node before each integration period begins. This reset operation, triggered by a reset pulse, ensures that the integration starts from a known zero state, preventing dark current from the previous frame from contaminating the current measurement.
Solution Approach 2:
The pixel circuit employs periodic reset pulses synchronized with the integration timing. These periodic reset operations occur at the start of each integration period, creating a regular clearing cycle that prevents dark current accumulation while allowing full integration of the desired signal during the inter-pulse interval.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves reduced leakage current and noise, enabling faster image capture with higher sensitivity and a wider dynamic range, while maintaining a smaller pixel size and minimizing motion artifacts.
Implementation Method 1
each comprising a photodiode
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A low leakage binned pixel (P9, P10) is provided. The pixel comprises a photodiode (502), a bin transistor (501) and an output amplifier circuit (530). The photodiode has an anode and a cathode, the anode to collect electrons generated by light or by other form of ionising radiation, e.g. electrons. The bin transistor has a first terminal coupled to the cathode of the photodiode; a second terminal, configured to be coupled to a first terminal of a voltage reset switch (VRST) transistor (50); and a gate, configured to be coupled to a controller to receive a bin signal. The output amplifier circuit has an input and an output (OUT), wherein the input is coupled to the cathode of the photodiode and to the second terminal of the bin transistor. A multi-pixel binned circuit, an image sensor and a camera are also provided.