Semiconductor Bio-Sensor Integration with CMOS via Sacrificial Oxide

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Solution Overview

Problem

The integration of semiconductor bio-sensors with CMOS devices is challenging due to the vulnerability of thin insulator and conductor layers to damage during the CMOS process, necessitating a method to protect and manufacture bio-sensors effectively within this context.

Innovation Solution

A method involving the sequential formation of dielectric and conductive layers, with specific etching processes to create cavities and vias, followed by passivation, allowing for the integration of bio-sensors with CMOS devices on a single wafer, ensuring protection and functionality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If bio-sensors are integrated with CMOS devices on a single wafer, then productivity and device integration are improved, but the thin insulator and conductor layers of bio-sensors are vulnerable to damage during the CMOS process

Engineering Contradiction:
Improvedevice integrationVSAvoidlayer integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A sacrificial oxide layer is introduced as an intermediary between the bio-sensor layers and the CMOS process environment. This sacrificial layer absorbs the harsh etching conditions, protecting the underlying thin insulator and conductor layers of the bio-sensor during CMOS fabrication while enabling wafer-level integration

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The method applies beforehand cushioning by forming a protective sacrificial oxide layer prior to the CMOS processing steps. This pre-established protective barrier cushions the vulnerable bio-sensor layers against damage from subsequent etching and processing operations in the CMOS fabrication sequence

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Ease of manufacture

If standard CMOS processing is applied to bio-sensors, then manufacturing complexity is reduced, but the thin insulator and conductor layers are easily damaged

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidlayer damage
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The sacrificial oxide layer serves as a mediator that allows standard CMOS processing to be applied without directly exposing the thin bio-sensor layers to harmful etchants. It absorbs the harmful effects while enabling the use of conventional manufacturing processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The method converts the potentially harmful etching processes into a beneficial protective mechanism. The sacrificial oxide layer is deliberately designed to be etched away, using the harmful etchants to remove the sacrificial layer while leaving the underlying bio-sensor layers protected and intact

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the reliable integration and protection of bio-sensors within the CMOS process, maintaining their integrity and functionality, thus facilitating their use alongside other semiconductor devices.

Implementation Method 1

forming cavities into the fourth dielectric layer by an isotropic etch

Methodology Applied
Scientific EffectIsotropic etching:

Implementation Method 2

forming vias through the cavities by an anisotropic etch

Methodology Applied
Scientific EffectAnisotropic etching:

Data Source

PatentUS8357547B2Semiconductor bio-sensors and methods of manufacturing the same
Publication Date: 2013.01.22 MACRONIX INTERNATIONAL CO LTD
  • US8357547B2 patent drawing
  • US8357547B2 patent drawing
  • US8357547B2 patent drawing

AI summary

A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.