BioFET Multi-Tiered Micro Well for Parasitic Capacitance Reduction
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Solution Overview
Problem
The fabrication and operation of biological field-effect transistors (BioFETs) face challenges due to compatibility issues between semiconductor fabrication processes and biological applications, particularly related to parasitic capacitances, high aspect ratio etching, and sensitivity to misalignment, which limit device sensitivity and density.
Innovation Solution
A multi-tiered micro well is formed over the sensing surface at the gate electrode or gate dielectric of BioFETs using CMOS-compatible processes, reducing antenna effect damage and allowing for higher device density without minimum sensing plate dimension limitations, and enabling optional replacement of gate dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor fabrication processes are used for BioFETs, then manufacturing compatibility is maintained, but parasitic capacitances increase and device sensitivity deteriorates
Solution Approach 1:
The gate structure is segmented into multiple tiers with varying widths, creating a multi-tiered micro well architecture. This segmentation allows the sensing surface to be divided into distinct functional zones that reduce parasitic capacitance while maintaining manufacturing compatibility
Solution Approach 2:
The invention transitions from a conventional planar gate structure to a three-dimensional multi-tiered micro well structure. By adding the vertical dimension with multiple tiers of different widths, the design reduces parasitic capacitance without compromising manufacturing process compatibility
2Manufacturing precision
If high aspect ratio etching is used to increase device density, then manufacturing precision improves, but charge-induced damage increases and reliability worsens
Solution Approach 1:
The etching process is segmented into multiple stages, creating a multi-tiered structure with progressive width reductions. This segmentation breaks down a single high aspect ratio etch into multiple lower aspect ratio etching steps, reducing charge-induced damage while achieving high device density
Solution Approach 2:
The multi-tiered structure is prepared in advance through sequential etching steps before final device operation. Each tier is formed with controlled dimensions to preemptively reduce the aspect ratio and minimize charge-induced damage during subsequent processing
3Productivity
If minimum sensing plate dimension limitations are imposed, then manufacturing complexity is reduced, but device density decreases and productivity worsens
Solution Approach 1:
The sensing structure extends into the vertical dimension with multiple tiers, allowing increased device density without reducing the minimum sensing plate dimension. The multi-level architecture provides additional sensing area while maintaining manufacturability
Solution Approach 2:
The multi-tiered micro well structure nests multiple sensing zones within a compact footprint. Each tier is nested within the previous tier, creating a space-efficient structure that increases device density without requiring smaller minimum sensing plate dimensions
4Manufacturing precision
If misalignment sensitivity is high, then manufacturing precision requirements increase, but ease of manufacture deteriorates
Solution Approach 1:
The gate structure is segmented into multiple tiers with progressive width reductions, creating self-aligning features at each level. This segmentation provides multiple alignment reference points that reduce overall misalignment sensitivity and ease manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the sensitivity and reliability of BioFETs by reducing parasitic capacitances, minimizing charge-induced damage, and allowing for more aggressive etching processes, resulting in a higher process window and improved alignment tolerance, thus enabling more complex interconnect routing and integration options.
Implementation Method 1
BioFETs are a type of biosensor that includes a transistor for electrically sensing biomolecules or bio-entities
Data Source
AI summary
The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a plurality of micro wells having a sensing gate bottom and a number of stacked well portions. A bottom surface area of a well portion is different from a top surface area of a well portion directly below. The micro wells are formed by multiple etching operations through different materials, including a sacrificial plug, to expose the sensing gate without plasma induced damage.