BioFET Cascade Readout Using Time-Domain Digital Counting
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Solution Overview
Problem
Biosensors that utilize transistors face challenges with analog signal processing, as these signals are prone to noise and require significant power, and the integration of analog-to-digital converters increases chip cost and die area.
Innovation Solution
A digital time domain readout circuit for bioFET sensors is developed, which uses digital components to reduce power consumption and die area by quantifying signals from bioFET sensors through logic gates and counting modules, enabling efficient detection of biomolecules without the need for analog signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog signal processing is used for bioFET sensors, then signal detection capability is maintained, but power consumption increases and die area expands
Solution Approach 1:
The patent replaces analog signal processing circuits with a digital time-domain readout circuit that uses logic gates and counters. This substitution eliminates the need for analog-to-digital converters and analog signal conditioning circuits, thereby reducing power consumption while maintaining detection capability through digital timing measurements of sensor response.
Solution Approach 2:
The patent changes the measurement parameter from analog voltage/current levels to time-domain characteristics. By measuring the time it takes for the sensor output to reach certain threshold levels and using this timing information for detection, the system achieves accurate measurement with digital circuits that consume less power than analog processing circuits.
2Measurement precision
If analog-to-digital converter is integrated, then digital detection signal is produced, but chip cost and die area increase
Solution Approach 1:
The patent extracts and eliminates the analog-to-digital converter from the sensor readout system. Instead of converting the analog sensor output to digital using a dedicated ADC circuit, the system directly processes the analog signal in the time domain using digital logic gates, thereby removing the ADC component and its associated die area while still producing digital detection signals.
Solution Approach 2:
The patent substitutes the ADC circuit with a time-domain digital processing system using logic gates and counters. This replacement eliminates the need for complex analog-to-digital conversion hardware, significantly reducing die area while maintaining digital output capability through timing-based measurement and digital counting.
3Ease of operation
If analog signal processing circuitry is used, then signal readout is achieved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog signal processing circuitry with a simpler digital time-domain readout circuit consisting of logic gates and counters. This substitution simplifies the overall device architecture by eliminating the need for analog amplifiers, filters, and ADCs, while maintaining ease of operation through digital signal processing and timing measurements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces power consumption and die area while providing accurate digital detection signals, enhancing the efficiency and cost-effectiveness of bioFET sensor systems.
Implementation Method 1
Biosensors that include transistors are sensors that electrically sense charges, photons, and mechanical properties of bio-entities or biomolecules
Data Source
AI summary
Various bioFET sensor readout circuits and their methods of operation are described. A readout circuit includes a plurality of logic gates coupled in cascade, a delay extractor, and a counting module. Each logic gate of the plurality of logic gates includes at least one bioFET sensor. The delay extractor is designed to generate a pulse-width signal based on a time difference between an output signal from the plurality of logic gates and a reference signal. The counting module is designed to receive the pulse-width signal and output a digital count corresponding to a width of the pulse-width signal.