BioFET Well Structure Etch Stop Layer Dimension Control
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Solution Overview
Problem
The fabrication of BioFETs faces challenges due to compatibility issues between semiconductor fabrication processes and biological applications, leading to non-uniform sensing surfaces and unstable sensing signals, primarily due to difficulties in controlling the dimensions of the well formed in the semiconductor structure during manufacturing.
Innovation Solution
A method for forming a BioFET using a complementary metal-oxide-semiconductor (CMOS) process flow, where a gate structure is formed over a substrate, source and drain regions are created, and a channel region is interposed by a sensing film with a well formed over it, utilizing etch stop layers to control the well dimensions and ensure uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional semiconductor fabrication processes are used to form the well structure, then manufacturing compatibility is improved, but the dimensional control of the well deteriorates leading to non-uniform sensing surfaces
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the sensing film and the underlying layers. This etch stop layer serves as a precise termination point for the etching process that forms the well, enabling accurate dimensional control of the well structure while maintaining compatibility with standard CMOS fabrication processes. The etch stop layer is selectively removed to define the well depth, ensuring uniform sensing surfaces across the substrate.
2Device complexity
If the well dimensions are not precisely controlled, then manufacturing complexity is reduced, but the stability of sensing signals deteriorates
Solution Approach 1:
The etch stop layer is deposited in advance during the film stacking process, before the well formation etching step. This preliminary placement of the etch stop layer pre-defines the future well dimension, allowing the subsequent etching process to proceed with standard parameters while achieving precise dimensional control. This approach maintains simple manufacturing procedures while ensuring stable sensing signals through uniform well structures.
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a gate structure over a first surface of the substrate, and a source region and a drain region in the substrate adjacent to the gate structure. The semiconductor structure further comprises a channel region interposing the source and drain regions and underlying the gate structure. The semiconductor structure further comprises a first layer over a second surface of the substrate opposite to the first surface, and a second layer over the first layer. The semiconductor structure further comprises a sensing film over the channel region and at least a portion of the first and second layers, and a well over the sensing film and cutting off the first layer and the second layer.