BIOS-BMC Memory-Mapped I/O for Faster Server Startup
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Solution Overview
Problem
The increasing complexity of server configurations necessitates more GPIO usage, leading to waste and increased startup times due to high latency in GPIO or KCS channel interactions between BIOS and BMC/CPLD, which are currently used for firmware cooperation.
Innovation Solution
Implementing a method that uses initial memory mapping IO to obtain a target memory mapping IO with low latency, allowing BIOS to interact with BMC and CPLD efficiently by segmenting and initializing regions, writing arbitration mechanisms, and using IPMI command channels to reduce interaction time and save GPIO resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GPIO or KCS channel is used for firmware interaction, then firmware communication is achieved, but startup time increases due to high latency
Solution Approach 1:
The patent replaces the mechanical GPIO pin-based communication system with a memory-mapped I/O system that uses CPU memory access mechanisms. This substitution eliminates the high latency inherent in GPIO polling and KCS channel protocols by utilizing the CPU's native memory access capabilities, thereby reducing startup time while maintaining reliable firmware communication between BIOS, BMC, and CPLD.
2Adaptability or versatility
If GPIO quantity increases to support complex configuration, then more functions are enabled, but GPIO resources are wasted
Solution Approach 1:
The patent transitions from a one-dimensional GPIO pin-based communication approach to a multi-dimensional memory-mapped I/O system. By mapping firmware interaction to memory addresses rather than physical pins, the system can support complex configuration functions without proportionally increasing physical GPIO usage. Multiple communication channels and data types can coexist in the memory space without requiring additional physical pins.
3Loss of time
If memory mapping IO is used for firmware interaction, then interaction latency is reduced, but system complexity increases
Solution Approach 1:
The patent leverages the CPU's existing memory management and I/O capabilities to create a universal communication interface for all firmware components. The memory-mapped I/O system serves multiple functions: data transmission, configuration, status monitoring, and coordination between BIOS, BMC, and CPLD. This multi-functionality is achieved by reusing existing CPU memory access mechanisms rather than introducing entirely new communication hardware, thereby limiting the increase in system complexity.
Data Source
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AI summary
Provided in the present application are a firmware interaction method and apparatus, and a server and a storage medium. The method is applied to a server, the server comprising a plurality of pieces of firmware, which are a central processing unit (CPU), a basic input/output system (BIOS) and a baseboard management controller (BMC). The method comprises: at a power-on self-test stage after a server is powered on, acquiring an initial memory mapping IO from a CPU by means of a BIOS; performing an initialization operation on the initial memory mapping IO by means of the BIOS to obtain a target memory mapping IO; and using the target memory mapping IO to interact with a BMC by means of the BIOS.