BIOS Cache Partitioning for Code Size Limitations

Solution Overview

Problem

The challenge in initializing a computer system during boot mode is the limitation on BIOS code size due to cache eviction constraints, which complicates the implementation of the no-eviction mode and increases BIOS runtime, especially in systems with smaller caches.

Innovation Solution

The solution involves partitioning the cache memory into readable and writeable ways, using model-specific registers to control cache eviction, and entering a no-modified-data-eviction mode to protect modified data while allowing eviction of readable data, thereby enabling efficient execution of BIOS code without size limitations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If no-eviction mode is used to protect cache lines, then data reliability is improved, but BIOS code size is limited and runtime increases

Engineering Contradiction:

Improvedata reliabilityVSAvoidBIOS code size limitation

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The cache is segmented into multiple ways, with specific ways designated for read-only code storage and other ways for read/write data storage. This segmentation allows the read-only code to be protected from eviction while allowing flexibility in data management, thereby supporting larger BIOS code sizes without compromising data reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different eviction policies are applied to different segments of the cache. Read-only code regions have eviction disabled, while data regions allow eviction. This local differentiation enables the system to maintain reliability for code while optimizing performance for data, resolving the contradiction between code size and runtime.

Inventive Principle:

Principle #3Local quality

2Reliability

If no-eviction mode is used to protect cache lines, then data reliability is improved, but BIOS runtime increases

Engineering Contradiction:

Improvedata reliabilityVSAvoidBIOS runtime

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The cache is segmented into multiple ways, with specific ways designated for read-only code storage and other ways for read/write data storage. This segmentation allows the read-only code to be protected from eviction while allowing flexibility in data management, thereby supporting larger BIOS code sizes without compromising data reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different eviction policies are applied to different segments of the cache. Read-only code regions have eviction disabled, while data regions allow eviction. This local differentiation enables the system to maintain reliability for code while optimizing performance for data, resolving the contradiction between code size and runtime.

Inventive Principle:

Principle #3Local quality

3Adaptability or versatility

If cache-as-RAM is used before system memory is available, then initialization capability is improved, but code size is limited by cache capacity

Engineering Contradiction:

Improveinitialization capabilityVSAvoidBIOS code size

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The cache is segmented into multiple ways, with specific ways designated for read-only code storage and other ways for read/write data storage. This segmentation allows the read-only code to be protected from eviction while allowing flexibility in data management, thereby supporting larger BIOS code sizes without compromising data reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The cache serves dual purposes: as a read-only code storage during initialization and as a read/write data storage. By enabling the cache to fulfill multiple functions through way partitioning, the system can support larger BIOS code sizes while maintaining initialization capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10175992B2Systems and methods for enhancing BIOS performance by alleviating code-size limitations

Publication Date: 2019.01.08 INTEL CORP

AI summary

Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.