BIOS Core Latency Selection for Multi-Core Processors
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Solution Overview
Problem
Existing information handling systems face inefficiencies in processing and communication due to the inability to optimally manage latency across multiple processor cores, leading to suboptimal performance in resource utilization.
Innovation Solution
A method where the BIOS calculates latency for each processor core in a multiple core processor and determines which cores to enable or disable based on latency, using a model-specific register to set the appropriate cores as enabled or disabled, thereby optimizing core usage for best latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all processor cores are enabled, then processing capacity is maximized, but latency increases due to resource contention and suboptimal core selection
Solution Approach 1:
The patent applies local quality by selecting and enabling only specific processor cores based on their individual latency characteristics. Instead of treating all cores uniformly, the system identifies cores with optimal latency properties (first subset) and enables only those, while disabling cores with higher latency (second subset). This localized differentiation optimizes latency performance by matching core selection to specific performance requirements.
2Loss of time
If processor cores are selectively enabled based on latency, then latency is optimized, but system complexity increases due to latency calculation and core selection logic
Solution Approach 1:
The patent implements preliminary action by having the BIOS calculate latency values for all processor cores during the boot-up phase before the operating system loads. This pre-calculation stores latency data in a data structure, eliminating the need for complex real-time latency measurement and core selection logic during system operation. The BIOS's preliminary work simplifies the overall system architecture while achieving optimized latency performance.
3Loss of time
If latency calculation is performed for all processor cores, then optimal core selection is achieved, but processing time during initialization increases
Solution Approach 1:
The patent applies preliminary action by performing latency calculations during the BIOS initialization phase, which occurs before the operating system begins its execution. By completing these calculations upfront during boot-up, the system avoids the need for time-consuming latency measurement during normal operation or application execution. This timing strategy accepts that initialization time can be invested in advance to achieve performance optimizations during the actual work load.
Data Source
AI summary
An information handling system includes a model-specific register and a basic input/output system (BIOS). The BIOS receives a selection of a number of processor cores to have enabled in a multiple core processor. In response to the reception of the selection of the number of processor cores to have enabled, the BIOS calculates a different latency for each of a plurality of processor cores in the multiple core processor. Based on the calculated different latency for each of the processor cores, the BIOS determines a first subset of the processor cores to enable and a second subset of the processor cores to disable. The BIOS sets bits in the model-specific register to indicate that the first subset of the processor cores is enabled and the second subset of the processor cores is disabled.