Early BIOS CPU P-State Control for Boot Power Reduction
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Solution Overview
Problem
Current information handling systems face high boot power consumption due to unmanaged CPU power excursions during the BIOS power-on-self-test (POST) phase, leading to thermal design power (TDP) levels that are challenging for power budgeting and can result in oversized power supply units (PSUs) and high recommended power cap limits.
Innovation Solution
Implementing early BIOS-controlled CPU P-states to limit CPU power during boot using a power state limiting mechanism, which calculates an optimized boot power allocation (BPA) to constrain power usage only until power management configurations are complete, thereby reducing boot power consumption and preventing uncontrolled power excursions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If early BIOS-controlled CPU power limiting is implemented, then boot power consumption is reduced, but system boot time may be extended
Solution Approach 1:
The BIOS performs preliminary power state configuration during the POST phase by reading power state limiting indicators and values from NVRAM before CPU operation begins. This preliminary action sets up power constraints in advance, allowing the CPU to operate at reduced power states during boot without requiring runtime intervention, thus reducing overall boot power consumption while minimizing time penalty
Solution Approach 2:
The system dynamically changes CPU operating parameters by programming power state values (P-states) based on indicators read from NVRAM. The BIOS modifies CPU frequency and voltage parameters to match the configured power state limiting, enabling flexible adjustment between power consumption and performance during the boot process
2Power
If power state limiting is enabled during boot, then power budgeting is improved, but CPU performance during boot is constrained
Solution Approach 1:
The boot process is segmented into distinct phases: POST phase where power state limiting is active and optimized boot power allocation applies, and post-checkpoint phase where full CPU performance is restored. This segmentation allows the system to optimize power consumption during the critical POST phase while maintaining full performance for application workloads, effectively resolving the contradiction between power budgeting and performance
Solution Approach 2:
The power state limiting mechanism is dynamic rather than static, allowing the system to adapt CPU power constraints based on real-time conditions. The BIOS checkpoint event serves as a dynamic threshold that automatically transitions the system from power-constrained mode to full-performance mode, enabling the system to optimize power budgeting when needed while maintaining performance when power is available
Data Source
AI summary
Systems and methods for reduced boot power consumption using early BIOS controlled CPU power states to enhance power budgeting and allocation. An information handling system may include a server. The server may include a central processing unit (CPU), a memory, a non-volatile random-access memory (NVRAM) device, a performance state (P-state) limiting indicator stored in the NVRAM device, a P-state value stored in the NVRAM, and a basic input/output system (BIOS) stored in the memory. The BIOS may read a power state limiting indicator stored in the NVRAM device and when the power state limiting indicator indicates that power state limiting is enabled, read a power state value stored in the NVRAM, and program the power state of the CPU to the power state value to cause the CPU to limit power supplied to the CPU to the power state value.