BIOS Fault Localization Through Identifier-Mapped Data Sub-Codes

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Solution Overview

Problem

Existing BIOS problem analysis methods are inefficient due to reduced boot-up speed and inconsistent problem detection when the debugging function is enabled or disabled, making it difficult to quickly and accurately locate complex issues.

Innovation Solution

Construct functional modules based on historical data, divide data codes into sub-codes, establish a correspondence with identifier information, and store target identifier information in a memory to quickly locate abnormal data sub-codes during BIOS operation anomalies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the debugging function is enabled to locate BIOS problems, then problem detection capability is improved, but boot-up speed deteriorates

Engineering Contradiction:
Improveproblem detection capabilityVSAvoidboot-up speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments the boot-up process into multiple phases and identifies specific checkpoint moments where problem detection should occur. By dividing the debugging process into discrete checkpoints rather than continuous monitoring, the system maintains problem detection capability while minimizing impact on boot-up speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary problem detection by checking for the presence of checkpoint information before full debugging is activated. This preliminary action allows the system to identify obvious issues without enabling the complete debugging function, thus maintaining fast boot-up while still providing problem detection for critical issues.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the debugging function is enabled to improve problem detection, then reliability is improved, but time consumption increases

Engineering Contradiction:
Improveproblem detection accuracyVSAvoidtime consumption
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts and records key checkpoint information (such as register states, memory contents, and execution flags) at critical moments during boot-up. By taking out only the essential diagnostic data rather than logging all operations, the system achieves reliable problem detection while minimizing time consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements partial debugging by selectively enabling problem detection at specific checkpoints rather than throughout the entire boot-up process. This partial action provides sufficient diagnostic information for most problems while avoiding the time penalty of comprehensive debugging.

Inventive Principle:
Principle #16Partial or excessive action

3Difficulty of detecting and measuring

If serial port information copying is performed to analyze problems, then problem analysis capability is improved, but boot-up speed deteriorates

Engineering Contradiction:
Improveproblem analysis capabilityVSAvoidboot-up speed
Core Design Contradiction:
Difficulty of detecting and measuringVSSpeed

Solution Approach 1:

The patent performs preliminary copying of essential serial port information at checkpoint moments during boot-up, rather than continuous copying. This preliminary action captures critical diagnostic data while minimizing the time spent on information copying, thus maintaining problem analysis capability without severely impacting boot-up speed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts only the most critical serial port information at each checkpoint (such as error codes, status flags, and key register values) rather than copying all serial port data. This selective extraction maintains problem analysis capability while reducing the time consumption of information copying.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12423202B2BIOS problem positioning method and apparatus, and computer readable storage medium
Publication Date: 2025.09.23 INSPUR SUZHOU INTELLIGENT TECH CO LTD
  • US12423202B2 patent drawing
  • US12423202B2 patent drawing
  • US12423202B2 patent drawing

AI summary

Disclosed in embodiments of the present application are a BIOS problem locating method and apparatus, and a medium. The method includes: constructing functional modules according to historical sample data; according to node information corresponding to each functional module, dividing data codes corresponding to the functional modules into data sub-codes; determining target identifier information according to correspondence between the data sub-codes and identifier information; when a problem occurs to a certain data sub-code, storing the target identifier information to a preset memory; and if an anomaly occurs to BIOS operation, according to the target identifier information recorded in the memory, quickly locating the abnormal target data sub-code.