BIOS Integrity Verification via Event-Based Interrupts

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Solution Overview

Problem

Existing methods for securing a computing system's BIOS struggle to balance accessibility for upgrades with protection against unauthorized tampering, as moving BIOS storage onto the microprocessor die complicates upgrades and encryption-based solutions degrade system performance.

Innovation Solution

A technique involving a BIOS ROM with plaintext contents and an encrypted message digest, using a symmetric key algorithm, coupled with an event detector and tamper detector to interrupt and verify the integrity of the BIOS during specific events, ensuring secure operation without degrading performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If BIOS storage is moved onto the microprocessor die to protect against tampering, then security is improved, but ease of upgrade deteriorates

Engineering Contradiction:
ImproveBIOS securityVSAvoidBIOS upgrade capability
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention separates BIOS storage into two distinct locations: plaintext BIOS contents stored in external BIOS ROM for easy upgrades, and cryptographic verification data (encrypted message digest and key) stored on the microprocessor die for security. This segmentation allows each component to fulfill its specific function without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces an intermediary verification mechanism where the microprocessor die stores cryptographic credentials that mediate between the external BIOS ROM and the system. The crypto/hash unit on the die verifies BIOS integrity by comparing message digests, acting as a trusted intermediary that enables secure external storage while maintaining upgradeability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If encryption-based solutions are used to protect BIOS contents, then security is improved, but system performance deteriorates

Engineering Contradiction:
ImproveBIOS protectionVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The invention extracts only the essential cryptographic verification data (encrypted message digest and symmetric key) and stores it on the microprocessor die, while leaving the bulk plaintext BIOS contents in external storage. This extraction minimizes the amount of data requiring cryptographic operations, thereby maintaining security while preserving system performance.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system performs preliminary verification by comparing message digests before full BIOS execution. The encrypted message digest stored on the die allows for quick verification of BIOS integrity without requiring decryption of the entire BIOS contents, thus maintaining performance while ensuring security.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If plaintext BIOS contents are stored externally for easy access, then ease of operation is improved, but vulnerability to tampering increases

Engineering Contradiction:
ImproveBIOS accessibilityVSAvoidtampering risk
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The system performs preliminary integrity verification by comparing message digests before allowing BIOS execution. The encrypted message digest stored on the microprocessor die serves as a pre-computed verification credential that checks BIOS integrity in advance, preventing tampered BIOS from executing while maintaining easy external access.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention implements a feedback mechanism where the crypto/hash unit continuously verifies BIOS integrity by comparing the current BIOS message digest against the stored encrypted message digest. This feedback loop detects any tampering attempts and prevents execution of compromised BIOS, maintaining security while allowing external storage.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10049217B2Event-based apparatus and method for securing bios in a trusted computing system during execution
Publication Date: 2018.08.14 VIA TECH INC
  • US10049217B2 patent drawing
  • US10049217B2 patent drawing
  • US10049217B2 patent drawing

AI summary

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a fuse array access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.