BIOS Integrity Verification via Event-Driven Interrupts

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Solution Overview

Problem

Existing methods for securing a computing system's BIOS struggle to balance accessibility for upgrades with protection against unauthorized tampering, as moving BIOS storage onto the microprocessor die complicates upgrades and encryption-based solutions degrade system performance.

Innovation Solution

A technique involving a BIOS ROM with plaintext contents and an encrypted message digest, using a symmetric key algorithm, coupled with an event detector and tamper detector to interrupt and verify the integrity of the BIOS during specific events, ensuring secure operation without degrading performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If BIOS storage is moved onto the microprocessor die, then protection against tampering is improved, but ease of upgrade deteriorates

Engineering Contradiction:
Improveprotection against tamperingVSAvoidease of upgrade
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention separates the BIOS storage into two parts: the main BIOS code remains in external ROM for easy upgradability, while a small verification module is integrated into the microprocessor die. This segmentation allows the system to maintain tamper protection capabilities without sacrificing the ability to easily upgrade the BIOS by simply replacing the external ROM chip.

Inventive Principle:
Principle #1Segmentation

2Reliability

If encryption-based solutions are used to protect BIOS, then security is improved, but system performance deteriorates

Engineering Contradiction:
ImprovesecurityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Instead of encrypting the entire BIOS code which would require continuous decryption operations and degrade performance, the invention applies encryption only to a small message digest (hash) of the BIOS. This partial application of encryption provides sufficient security verification while maintaining high system performance during normal operation.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The message digest is pre-calculated and stored alongside the BIOS code in the external ROM. This preliminary action allows the system to perform quick verification by comparing the pre-stored digest with a newly calculated one, rather than performing expensive encryption/decryption operations on the entire BIOS during each verification.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If on-die memory is used to store encrypted BIOS, then tamper protection is improved, but power consumption and cost increase

Engineering Contradiction:
Improvetamper protectionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The invention extracts the BIOS storage function from the microprocessor die and places it in external ROM. Only the essential verification logic remains on-die, which consumes minimal power. This extraction eliminates the need for power-hungry on-die encrypted storage while maintaining tamper protection through the message digest verification mechanism.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10095868B2Event-based apparatus and method for securing bios in a trusted computing system during execution
Publication Date: 2018.10.09 VIA TECH INC
  • US10095868B2 patent drawing
  • US10095868B2 patent drawing
  • US10095868B2 patent drawing

AI summary

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of an APIC access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.