BIOS Integrity Verification via Event-Triggered Interrupts

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Solution Overview

Problem

Existing methods for securing a computing system's BIOS struggle to balance accessibility for upgrades with protection against unauthorized tampering, as moving BIOS storage onto the microprocessor die complicates upgrades and encryption-based solutions degrade system performance.

Innovation Solution

A system that includes a BIOS ROM with plaintext contents and an encrypted message digest, using a symmetric key algorithm, coupled with an event detector and tamper detector to interrupt and verify the integrity of the BIOS during power glitches or other events, ensuring only authorized operation by comparing message digests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If BIOS storage is moved onto the microprocessor die to protect against tampering, then security is improved, but ease of upgrade deteriorates

Engineering Contradiction:
ImproveBIOS securityVSAvoidBIOS upgradeability
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The invention separates BIOS storage into two distinct locations: plaintext BIOS contents stored in external ROM for easy upgradeability, and cryptographic verification data (encrypted message digest and key) stored in secure internal memory on the microprocessor die for tamper protection. This segmentation allows each component to fulfill its specific function without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces an intermediary cryptographic verification mechanism that mediates between the external plaintext BIOS storage and the microprocessor. The encrypted message digest stored in secure internal memory acts as a mediator that verifies the integrity of the external BIOS without requiring the BIOS to be physically embedded in the processor.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If encryption-based solutions are used to protect BIOS contents, then security is improved, but system performance deteriorates

Engineering Contradiction:
ImproveBIOS protectionVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The invention applies different quality characteristics to different parts of the BIOS storage system. The BIOS contents are stored in plaintext in external ROM for fast access and system performance, while only the critical verification data (encrypted message digest and key) is stored in secure internal memory. This local differentiation of security requirements eliminates the performance penalty of encrypting the entire BIOS.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of encrypting the entire BIOS contents, the invention applies encryption only to the essential verification components (message digest and key). This partial application of encryption provides sufficient security protection while maintaining fast access to the plaintext BIOS contents during system operation.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10055588B2Event-based apparatus and method for securing BIOS in a trusted computing system during execution
Publication Date: 2018.08.21 VIA TECH INC
  • US10055588B2 patent drawing
  • US10055588B2 patent drawing
  • US10055588B2 patent drawing

AI summary

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a power glitch exceeding a specified threshold within a specified time period. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.