BIOS Processor Swap Detection for DDR Training Skip
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current DDR training processes in personal computers and servers are time-consuming and destabilizing, requiring calibration of DRAM channels during boot, which can lead to higher bit error rates and increased boot times, especially as system complexity increases, and there is no effective mechanism for BIOS to track processor changes without violating privacy or security concerns.
Innovation Solution
The proposed solution involves using Intel Trusted eXecution Technology (TXT) AC Module and Trusted Platform Module (TPM) to securely determine processor serial numbers without exposing them to general-purpose software, allowing BIOS to skip DDR training steps if no changes are detected, thereby reducing boot times and improving 'time to video' metrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DDR training calibration steps are performed during boot, then memory signal quality and timing are optimized, but boot time increases and system stability decreases
Solution Approach 1:
The patent performs DDR training calibration during manufacturing or initial setup, storing the calibrated parameters in non-volatile memory. During subsequent boot operations, the system retrieves pre-stored calibration parameters instead of performing full calibration, thereby eliminating the time-consuming calibration step while maintaining optimized memory performance and system stability.
2Productivity
If per DDR device calibration is performed across multiple parameters, then higher memory speeds and lower voltages are achieved, but memory training process time increases
Solution Approach 1:
The system performs comprehensive per-DDR device calibration during manufacturing or initial setup, storing the optimized parameters for multiple parameters (timing, voltage, frequency) in non-volatile memory. During normal operation, these pre-calibrated parameters are retrieved and applied, achieving high memory speeds and low voltages without the time penalty of repeated calibration.
Solution Approach 2:
The patent creates a copy of the calibrated parameters from the manufacturing process and stores them in non-volatile memory. This copied parameter set is then reused during boot operations, eliminating the need to repeat the time-consuming calibration process while maintaining the performance benefits of comprehensive calibration.
3Loss of time
If processor identifier is tracked to detect no-processor swap, then unnecessary DDR training can be avoided, but privacy and security concerns arise
Solution Approach 1:
The patent introduces a trusted platform module (TPM) or secure enclave as an intermediary to handle processor identifier tracking. This secure hardware component acts as a mediator between the BIOS and the processor, enabling the system to detect processor changes and skip DDR training when appropriate, while maintaining privacy and security by keeping the identifier tracking within the secure boundary.
Solution Approach 2:
The system uses self-service mechanisms where the processor or platform firmware automatically provides identifier information to the secure tracking mechanism without requiring external intervention. This allows the system to autonomously detect processor swaps and optimize boot time by skipping unnecessary DDR training, while maintaining security through the use of protected identifier storage and comparison mechanisms.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Memory channel training parameters are function of electrical characteristics of memory devices, processor(s) and memory channel(s). Training steps can be skipped if the BIOS can determine that the memory devices, motherboard and processor have not changed since the last boot. Memory devices contain a serial number for tracking purposes and most mother-boards contain a serial number. Many processors do not provide a mechanism by which the BIOS can track the processor. Described herein are techniques that allow the BIOS to track a processor and detect a swap without violating privacy/security requirements.