BIOS ROM Address Routing via MMIO and SPI Interfaces

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Solution Overview

Problem

Traditional BIOS systems are limited in accessing read-only memory (ROM) space due to chipset decoding range limitations, restricting their ability to address larger ROM sizes and leading to unused memory regions.

Innovation Solution

The implementation of an information handling system with a BIOS-accessible ROM divided into subregions, where the BIOS determines the appropriate communication interface to use based on the memory address, allowing access via MMIO for addresses within the decoding range and SPI for addresses outside, thereby expanding BIOS access to ROM space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a single communication interface is used for BIOS access to ROM, then the system structure is simple, but the BIOS cannot access memory regions outside the chipset decoding range

Engineering Contradiction:

ImproveBIOS memory access rangeVSAvoidcommunication interface structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The BIOS is designed to perform multiple functions by accessing different communication interfaces (MMIO and SPI) depending on the memory address being accessed. This allows a single BIOS system to handle both traditional MMIO addresses and extended SPI addresses, achieving universal access across the entire ROM space without requiring separate BIOS instances for each interface type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The BIOS acts as an intermediary layer between the processor and the ROM memory. It receives memory access requests from the processor, determines whether the target address falls within the MMIO decoding range or requires SPI interface access, and then routes the request through the appropriate communication interface. This mediation enables expanded memory access while maintaining a unified system architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If ROM size is increased to accommodate more components, then more components can be supported, but the chipset decoding range limitation prevents BIOS from addressing the entire ROM space

Engineering Contradiction:

ImproveROM capacityVSAvoidmemory addressability

Core Design Contradiction:

Quantity of substanceVSEase of operation

Solution Approach 1:

The ROM memory space is segmented into two distinct regions: the first subregion accessible through the traditional MMIO interface within the chipset decoding range, and the second subregion accessible through the SPI interface for addresses outside the decoding range. This segmentation allows the system to support expanded ROM capacity while maintaining compatibility with existing MMIO-based access patterns for traditional BIOS components.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system changes the communication parameter (interface type) based on the memory address parameter. When the BIOS receives a memory access request, it evaluates the address to determine whether to use the MMIO interface or the SPI interface. This parameter change enables the system to address the entire ROM space, including regions that would be inaccessible under traditional single-interface limitations.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If traditional MMIO interface is used for BIOS access, then compatibility with existing systems is maintained, but addresses outside the decoding range remain nonaddressable

Engineering Contradiction:

Improvememory address coverageVSAvoidunused memory space

Core Design Contradiction:

Adaptability or versatilityVSLoss of energy

Solution Approach 1:

Instead of expanding the MMIO decoding range to cover the entire ROM space (which would conflict with dedicated regions for other components), the patent inverts the approach by using the SPI interface for addresses outside the traditional MMIO range. This allows the MMIO interface to maintain its traditional addressing scheme and compatibility while the SPI interface handles the extended address space, effectively utilizing previously nonaddressable memory regions without disrupting existing system architecture.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS11392389B2Systems and methods for supporting BIOS accessibility to traditionally nonaddressable read-only memory space

Publication Date: 2022.07.19 DELL PROD LP

AI summary

An information handling system may include a processor and a read-only memory communicatively coupled to the processor and comprising a basic input/output system (BIOS)-accessible region of the read-only memory including a first subregion communicatively coupled to the processor via a first communications interface and a second subregion communicatively coupled to the processor via a second communications interface. The information handling system may also include the BIOS, configured to responsive to a read request from the processor to the BIOS-accessible region determine whether a memory address associated with the read request is within a decoding range of the first subregion, cause the processor to access the first subregion via the first communications interface if the memory address is within the decoding range, and cause the processor to access the second subregion via the second communications interface if the memory address is outside the decoding range.