BIOS Shared Memory Asynchronous Command Interface
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Solution Overview
Problem
Conventional BIOS communication with an embedded controller (EC) is inefficient due to the need to wait for the EC to complete processing before issuing new commands, leading to lower operational efficiency and increased probability of execution errors, especially given the significant difference in processing speeds between the CPU and EC.
Innovation Solution
A data processing apparatus that utilizes a shared memory to store command and returned data, allowing the BIOS unit to issue new commands without waiting for the EC to complete old ones, with the shared memory acting as a communication medium between the BIOS unit and the control unit, enabling asynchronous communication and high-speed data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the BIOS waits for the EC to complete processing before issuing new commands, then execution errors are reduced, but operational efficiency and performance deteriorate
Solution Approach 1:
The communication interface is segmented into separate write and read buffers within the shared memory. The write buffer allows the BIOS to issue commands without waiting for EC processing completion, while the read buffer stores results for later retrieval. This segmentation enables asynchronous communication, resolving the contradiction between reliability and productivity.
Solution Approach 2:
A shared memory structure acts as an intermediary between the BIOS and EC, decoupling their interaction. The BIOS writes commands to the write buffer and the EC reads them asynchronously, while results are written to the read buffer for BIOS retrieval. This intermediary mechanism allows continuous command issuance without waiting for EC completion, improving operational efficiency while maintaining execution reliability.
2Device complexity
If the BIOS communicates with the EC through conventional I/O ports, then device complexity is minimized, but data transfer speed and performance deteriorate
Solution Approach 1:
The communication interface merges memory access with I/O communication by using a shared memory structure that the BIOS can access through standard memory operations. This combining of memory and I/O functions eliminates the need for complex I/O port protocols while enabling high-speed data transfer through the memory interface, resolving the contradiction between device complexity and transfer speed.
3Adaptability or versatility
If data is transferred in 8-bit word length through ISA bus, then device compatibility is maintained, but processing speed and performance deteriorate
Solution Approach 1:
The patent transitions from one-dimensional I/O port communication to a two-dimensional shared memory structure with separate write and read buffers. This dimensional change allows the system to maintain compatibility with existing BIOS architectures while enabling parallel command issuance and result retrieval, effectively bypassing the 8-bit ISA bus speed limitation through memory-mapped I/O operations.
Data Source
AI summary
A data processing apparatus of a basic input/output system (BIOS) is provided. The data processing apparatus includes a BIOS unit, a share memory and a control unit. The BIOS unit writes command data into the share memory, wherein the command data includes identification data stored in an identification field. The control unit reads and performs the command data according to the identification data in the identification field. After the command data is performed, the control unit writes returned data into the share memory for the BIOS unit to read the returned data, wherein the returned data includes the execution result of the command data performed by the control unit and also includes the identification data.