Biosensor Device with C-Shaped Gate and CMOS Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing biosensor devices face challenges in manufacturing due to difficulty in controlling the etching depth of silicon oxide layers and inconsistency with standard CMOS fabrication, leading to variable yield and sensitivity issues.
Innovation Solution
A biosensor device with a substrate, a sensing transistor featuring a C-shaped gate structure and a main interface layer for biomolecule detection, which is manufactured using standard CMOS processes to enhance sensitivity and reduce environmental noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the bulk is etched for large depth to form the well, then the sensing element can be exposed, but the etching depth is difficult to control and requires additional processes
Solution Approach 1:
The patent applies preliminary action by forming the sensing element structure before bulk etching. Specifically, the semiconductor layer is deposited and patterned to define the sensing element shape and depth, then the bulk is etched away to expose this pre-formed structure. This eliminates the need for deep bulk etching to create the sensing element, as the structure is already in place.
Solution Approach 2:
The patent segments the sensing element formation process from the bulk etching process. The sensing element is created as a separate deposited layer (semiconductor layer 16) that can be independently controlled, while the bulk etching simply removes material to expose it. This segmentation allows independent optimization of each process.
2Manufacturing precision
If the SiO2 layer is etched to expose the poly layer, then the sensing element becomes accessible, but the remaining thickness of SiO2 layer is difficult to control and yield factor varies
Solution Approach 1:
The patent forms the semiconductor layer (sensing element) on the SiO2 layer before any etching processes. This preliminary formation of the sensing element with controlled thickness through deposition allows precise control of the remaining SiO2 layer thickness, as it simply needs to be etched away to expose the pre-formed sensing element.
3Ease of manufacture
If standard CMOS fabrication is used, then manufacturing cost is reduced, but the SiO2 layer etching process is inconsistent with standard CMOS
Solution Approach 1:
The patent segments the biosensor fabrication into standard CMOS-compatible steps (semiconductor layer deposition, patterning, metal layer formation) and a separate bulk etching step. This allows the majority of the process to follow standard CMOS fabrication, reducing cost, while only requiring one additional etching process to expose the sensing element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The biosensor device improves sensitivity by enhancing sensing signal strength and reduces manufacturing costs through standard CMOS fabrication, while minimizing environmental noise interference.
Implementation Method 1
a main interface layer disposed in the first opening for receiving biomolecules to be sensed
Implementation Method 2
enhancing the sensing signal strength... by improving electrical field effects
Data Source
AI summary
A biosensor device includes a substrate, a sensing transistor, an isolation layer and a main interface layer. The sensing transistor is formed on the substrate and including a bottom gate structure, a top gate structure and a semiconductor layer disposed between the bottom gate structure and the top gate structure. The bottom gate structure is electrically connected to the top gate structure. The isolation layer is formed on the sensing transistor for covering the sensing transistor, and includes a first opening. The main interface layer is disposed in the first opening for receiving biomolecules to be sensed. The main interface layer is electrically connected to the top gate structure.