Self-Aligned Biosensor FET for Noise Reduction

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Solution Overview

Problem

Field-effect transistors (FETs) face limitations in clinical applications due to noise, sensitivity, and reproducibility issues, particularly in dual-gate ISFETs, which are restricted to pH sensing and have challenges with mass production and stability.

Innovation Solution

A field-effect transistor design with a buried oxide layer, active patterns, and gate patterns that are self-aligned using a gate-first process, reducing noise and enabling multiple detection purposes, combined with a biosensor for enhanced sensitivity and stability, allowing for mass production and various detection capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a dual-gate ISFET structure is used to increase sensitivity, then sensing characteristics are improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvesensing characteristicsVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The device is divided into distinct functional regions including a first active region with channel, source and drain regions, and a second active region with channel, source and drain regions. This segmentation allows each region to be independently optimized and manufactured, reducing overall device complexity while maintaining enhanced sensing capabilities through the dual-gate configuration.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If traditional photolithography processes are used for manufacturing, then manufacturing precision can be achieved, but the number of process steps increases and productivity decreases

Engineering Contradiction:
Improvemanufacturing precisionVSAvoidproductivity
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

Gate patterns are formed first before the active patterns in a gate-first process sequence. This preliminary action of creating the gate structure early in the manufacturing process enables subsequent self-alignment of active regions to the gate, reducing the need for additional alignment steps and photolithography processes while maintaining high manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The gate pattern serves as a self-aligning reference for subsequent active pattern formation. The gate structure automatically defines the positional relationship between different device regions, eliminating the need for complex external alignment procedures and multiple photolithography steps, thereby improving productivity without sacrificing manufacturing precision.

Inventive Principle:
Principle #25Self-service

3Ease of manufacture

If channel region length is not accurately defined, then manufacturing is simpler, but noise increases due to electron scattering

Engineering Contradiction:
Improveease of manufactureVSAvoidnoise
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent replaces complex mechanical alignment systems with a self-aligning field-effect mechanism. The gate-first process creates an electric field configuration that automatically defines the effective channel length through field distribution, eliminating the need for precise mechanical dimensional control while reducing noise from electron scattering.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

4Adaptability or versatility

If multiple detection purposes are enabled through various active and gate patterns, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improvedetection capabilitiesVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The dual-gate ISFET structure with first and second active regions serves multiple detection functions simultaneously. The gate-first process creates a universal platform where different analyte detection capabilities can be implemented by modifying surface functionalization on the same basic device structure, enabling multi-functionality without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution significantly reduces noise, improves sensitivity and stability, and enables mass production of FETs, expanding their clinical applications beyond pH sensing by allowing multiple detection purposes and stable performance with various specimens.

Implementation Method 1

a gate insulating film disposed between the active pattern and the gate pattern

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

An ion-sensitive field-effect transistor (ISFET) is an electrochemical sensor capable of sensitively detecting a signal originating from an interaction between a biological sample and an analyte and accurately converting the signal into an electric signal

Methodology Applied
Scientific EffectField effect: Electric Field

Data Source

PatentUS10739301B2Field-effect transistor, biosensor comprising the same, method of manufacturing field-effect transistor, and method of manufacturing biosensor
Publication Date: 2020.08.11 KOREA INST OF SCI & TECH
  • US10739301B2 patent drawing
  • US10739301B2 patent drawing
  • US10739301B2 patent drawing

AI summary

Provided is a field-effect transistor that can reduce noise, be produced by a simplified manufacturing method, and also have a plurality of active patterns and gate patterns designed to be combinable according to a detection purpose. The field-effect transistor includes a lower silicon layer and a buried oxide layer disposed on the lower silicon layer; an active pattern disposed on the buried oxide layer and including a channel region, a source region, and a drain region; a gate pattern disposed on the active pattern to at least partially overlap the active pattern; a source electrode disposed in direct contact with the source region on the active pattern, and a drain electrode disposed in direct contact with the drain region on the active pattern; and a gate insulating film disposed between the active pattern and the gate pattern.