Self-Aligned Emitter-Base BiCMOS Transistor Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fabricating small bipolar transistors capable of amplifying electrical signals at high frequencies, such as 300 GHz, while integrating with 90 nm CMOS devices, is challenging due to parasitic capacitances and resistances, which affect cutoff frequency (Ft) and maximum oscillation frequency (Fmax).
Innovation Solution
A self-aligned bipolar transistor fabrication method involving a stack of films with selectively grown silicon layer stripes in slots between the intrinsic and extrinsic bases, using a self-aligned oxide mask and spacer formation to expose and etch the intrinsic base, allowing precise growth of silicon layer stripes that fill slots without overburdening, thereby reducing parasitic resistances and capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the transistor size is reduced to achieve high frequency operation, then the cutoff frequency and maximum oscillation frequency are improved, but the parasitic capacitances and resistances increase
Solution Approach 1:
The patent introduces a vertical slot structure extending through the extrinsic base layer, transforming the horizontal connection approach into a vertical three-dimensional configuration. This dimensional change reduces the parasitic capacitance area while maintaining electrical connectivity, directly addressing the contradiction between small size and reduced parasitic effects.
Solution Approach 2:
The patent applies selective oxidation to create localized oxide regions around the silicon link in the slot, providing targeted electrical isolation and reduced parasitic capacitance at critical interfaces. This local quality modification allows precise control of parasitic effects without affecting the overall transistor performance.
2Speed
If the transistor size is reduced to achieve high frequency operation, then the cutoff frequency and maximum oscillation frequency are improved, but the parasitic resistances increase
Solution Approach 1:
The vertical slot configuration provides a direct vertical current path through the extrinsic base layer, reducing the horizontal current path length and associated parasitic resistance. The three-dimensional structure enables shorter current paths while maintaining structural integrity.
Solution Approach 2:
The silicon link grown in the slot acts as an intermediary conductive path between the emitter and collector regions, providing a low-resistance vertical connection that bypasses the high-resistance horizontal paths through the extrinsic base, thereby reducing parasitic resistance.
3Manufacturing precision
If a self-aligned fabrication method is used to reduce misalignment, then the manufacturing precision is improved, but the device complexity increases
Solution Approach 1:
The patent employs self-aligned fabrication where the slot and oxide structures automatically define the position of the silicon link without requiring additional alignment steps. The extrinsic base layer itself serves as the alignment reference, eliminating the need for separate mask alignment procedures and reducing process complexity despite the three-dimensional structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the fabrication of transistors with improved cutoff and maximum oscillation frequencies by reducing parasitic resistances and capacitances, facilitating high-frequency signal amplification and integration with CMOS devices.
Implementation Method 1
A silicon layer stripe is then selectively grown on at least one of the exposed intrinsic base layer and extrinsic base layer in each of the first slot and the second slot
Data Source
AI summary
A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.