Biphase Signal Decoding Using Time-Varying Histograms for Jitter Rejection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing decoding technologies face challenges in effectively handling jitter and drift in biphase encoded signals, particularly in digital audio interfaces, where jitter rejection and synchronization are crucial but often incomplete, leading to inefficiencies in clock recovery and data decoding.
Innovation Solution
A time-varying histogram is constructed to track inter-arrival times of pulse edges, allowing for the identification of single, double, and triple length intervals, thereby enhancing jitter rejection and drift compensation without relying on phase locked loops, using a binary weighted frequency array to maintain histogram bins and discriminate between interval lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase locked loops are used for clock recovery and synchronization, then synchronization can be achieved, but the system becomes complex and jitter rejection is incomplete
Solution Approach 1:
The patent extracts the clock recovery function from complex phase locked loop systems and implements it through a simplified histogram-based interval analysis method. By focusing only on inter-pulse interval measurement and statistical analysis, the system achieves synchronization without the complexity of traditional PLL circuits.
Solution Approach 2:
The patent replaces the mechanical/electrical phase locked loop system with a digital signal processing approach using histogram analysis. The analog/physical synchronization mechanism is substituted with digital interval measurement and statistical comparison, reducing hardware complexity while maintaining synchronization reliability.
2Productivity
If traditional decoding methods are used, then decoding can be performed, but jitter and drift cause decoding errors
Solution Approach 1:
The patent implements feedback through histogram analysis of inter-pulse intervals. By continuously measuring intervals, building the histogram, and using the histogram to identify and correct jitter and drift effects, the system creates a closed-loop feedback mechanism that improves decoding accuracy without sacrificing speed.
Solution Approach 2:
The patent performs preliminary action by pre-building the histogram of inter-pulse intervals before actual decoding. This statistical preparation allows the decoder to quickly reference pre-computed interval distributions during decoding, maintaining high speed while having jitter and drift compensation data ready in advance.
3Measurement precision
If high precision clock recovery is achieved, then signal-to-noise ratio improves, but the system requires complex filtering and processing
Solution Approach 1:
The patent uses periodic action through the regular updating of the histogram structure at defined intervals. This periodic refresh of interval statistics provides continuous clock recovery precision without requiring complex continuous filtering, as the histogram is naturally updated in periodic cycles matching the signal structure.
Solution Approach 2:
The patent implements dynamics by making the histogram structure adaptive and time-varying. The histogram dynamically adjusts to reflect current signal conditions, allowing the system to maintain high measurement precision under varying jitter and drift conditions without fixed complex filtering parameters.
Data Source
AI summary
This application relates to decoding signals that carry clock and data information. In particular, it relates to construction a time-varying histogram of inter-arrival times between pulse edges and using the histogram to identify whether a pulse edge encodes a single length interval, a double length interval or some longer length interval. Further details and embodiments of the technology disclosed are provided in the drawings, detailed description and claims.