Coupled Bipolar Base and FET Gate Structure for CMOS Integration
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Solution Overview
Problem
Efficient integration of lateral bipolar transistors into the same device layer as field effect transistors in complementary metal oxide semiconductor (CMOS) process flows for semiconductor-on-insulator structures is a technical challenge.
Innovation Solution
A structure is designed with a bipolar transistor over a first back-gate well and a field effect transistor over an adjacent second back-gate well, where the gate structure of the FET is coupled to the base structure of the BT, allowing for a shared node without intervening elements, and independent or simultaneous biasing through back-gate terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lateral bipolar transistors are integrated into the same device layer as field effect transistors in CMOS process flows, then device integration efficiency is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the integrated circuit into distinct regions with separate back-gate wells - a first back-gate well for the bipolar transistor and a second back-gate well for the FET. This segmentation allows each transistor type to have optimized control structures while maintaining integration in the same device layer, thus improving integration efficiency without excessive complexity increase
Solution Approach 2:
The patent introduces separate back-gate wells as intermediary structures to independently control the bipolar transistor and FET. These back-gate wells act as mediators that enable precise control of each transistor type's characteristics, simplifying the manufacturing process by providing clear separation of control mechanisms despite intimate device integration
2Area of stationary object
If lateral bipolar transistors are integrated into the same device layer as field effect transistors, then surface area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
By segmenting the substrate into separate back-gate wells for bipolar and FET devices, the patent enables compact lateral integration that reduces overall surface area while maintaining distinct control regions. This segmentation allows standard CMOS fabrication processes to be used without requiring excessive manufacturing precision
Solution Approach 2:
The patent employs a universal back-gate well structure that serves multiple functions - it provides electrical isolation, enables independent biasing control, and facilitates compact device layout. This multi-functional approach reduces surface area while keeping manufacturing precision requirements within standard CMOS capabilities
3Loss of energy
If the gate structure is coupled to the base structure with a shared node, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges the FET gate structure with the bipolar transistor base structure by coupling them at a shared node. This merging eliminates the need for separate biasing circuits for the base and gate, reducing power consumption while the separate back-gate wells maintain manageable device complexity through independent control capability
Solution Approach 2:
The shared node between the FET gate and bipolar base serves multiple functions simultaneously - it acts as the gate control terminal for the FET, the base terminal for the bipolar transistor, and a common reference potential. This multi-functionality reduces power consumption without significantly increasing device complexity
Data Source
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AI summary
Embodiments of the disclosure provide a structure including a first back-gate well adjacent a second back-gate well. A bipolar transistor (BT) is over the first back-gate well and includes a base structure laterally between a set of emitter/collector (E/C) terminals and extending longitudinally away from the set of E/C terminals. A field effect transistor (FET) is over the second back-gate well and includes a gate structure laterally between a set of source/drain (S/D) terminals and extending longitudinally away from the set of S/D terminals toward the BT. The gate structure is coupled to the base structure.