Bipolar Clock Level Shifter for Reliable Transistor Turn-Off

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Solution Overview

Problem

Current level shifter circuits used in chopper amplifier applications often fail to effectively turn off transistors due to non-idealities, leading to signal leakage and distortion, especially at high temperatures, as they typically generate unipolar clock signals that do not adequately match the voltage levels required for proper transistor operation.

Innovation Solution

A level shifter circuit is designed to generate bipolar clock signals by using multiple transistor pairs and a clock generation circuit, allowing the clock signals to oscillate between two voltage levels, ensuring effective turn-on and turn-off of transistors by swinging in both polarities relative to the input signal, thereby reducing leakage and distortion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If unipolar clock signals are used in level shifter circuits, then the circuit structure is simple, but transistor turn-off effectiveness deteriorates leading to signal leakage and distortion

Engineering Contradiction:
Improvecircuit structureVSAvoidtransistor turn-off effectiveness
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent changes the voltage level parameters of the clock signal from unipolar to bipolar, allowing the signal to swing both above and below the input signal level. This parameter change enables the clock signal to properly turn on and off transistors across different voltage domains, resolving the reliability issue while maintaining circuit functionality

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Instead of using a traditional unipolar clock signal that only swings in one direction, the patent inverts the approach by using a bipolar clock signal that swings in both directions relative to the input signal. This inversion allows the clock signal to effectively control transistors in the level shifter circuit by providing both positive and negative voltage swings relative to the input signal level

Inventive Principle:
Principle #13The other way round (Inversion)

2Ease of manufacture

If unipolar clock signals are used, then the signal generation is simple, but signal leakage and distortion increase especially at high temperatures

Engineering Contradiction:
Improvesignal generationVSAvoidsignal leakage and distortion
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent modifies the clock signal parameters from unipolar to bipolar voltage levels, enabling the signal to swing both above and below the input signal level. This parameter change ensures that transistors are properly turned on and off, significantly reducing signal leakage and distortion even at high temperatures while maintaining manufacturing simplicity

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If voltage level matching is not implemented, then the circuit operation is simple, but transistor control effectiveness deteriorates

Engineering Contradiction:
Improvecircuit operationVSAvoidtransistor control effectiveness
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent implements voltage level matching by generating a bipolar clock signal whose voltage levels are specifically tailored to match the requirements of the transistors in the level shifter circuit. The clock signal swings from (Vin - VDD) to (Vin + VDD), ensuring proper transistor control across different voltage domains while maintaining ease of circuit operation

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10979052B2Level shifter circuit generating bipolar clock signals
Publication Date: 2021.04.13 TEXAS INSTRUMENTS INC
  • US10979052B2 patent drawing
  • US10979052B2 patent drawing
  • US10979052B2 patent drawing

AI summary

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.