BiCMOS Integration Reducing Masking Steps via Shared SiGe
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Solution Overview
Problem
BiCMOS fabrication processes require a high number of masking steps, leading to high costs and complex processing for high-performance devices, while simpler processes compromise device performance by lacking independently customized SiGe profiles for NPN and PNP devices.
Innovation Solution
A BiCMOS integration method that reduces masking steps by forming a shared SiGe layer and using a masking layer to define emitter regions for both NPN and PNP devices, allowing for simultaneous implantation of dopants and reducing the number of processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex process flow with high mask count (40-50 masking layers) is used to form SiGe heterojunction bipolar transistors, then high performance devices are achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent merges the formation of NPN and PNP bipolar devices into a single integrated process flow. Key process steps including SiGe layer deposition, emitter window formation, and dopant implantation are combined into shared sequences that simultaneously define both NPN and PNP device structures, reducing the total mask count from 40-50 layers to a significantly lower number while maintaining device performance
Solution Approach 2:
The patent creates universal process steps that serve multiple device types. For example, a single SiGe deposition process and masking sequence is designed to form both NPN and PNP device regions, allowing the same process equipment and parameters to be used for both complementary bipolar device types, thereby reducing manufacturing complexity and cost
2Ease of manufacture
If a simple process flow with reduced masking steps is used for co-implantation of undoped SiGe layer, then manufacturing cost is reduced, but device performance is compromised due to lack of independently customized SiGe profiles
Solution Approach 1:
The patent segments the SiGe processing into distinct, independently controllable steps. Separate SiGe deposition processes are performed for NPN and PNP devices, allowing independent optimization of SiGe profiles for each device type. This segmentation enables customized germanium content and layer thicknesses for each bipolar device type while using a reduced overall mask count compared to traditional approaches
Solution Approach 2:
The patent performs preliminary SiGe layer deposition and patterning actions before final device formation. By pre-forming the SiGe profiles with appropriate germanium content and thickness for each device type through separate deposition steps, the subsequent processing can proceed with fewer masking steps, as the critical SiGe structures are already in place and differentiated
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach lowers manufacturing costs, simplifies processing complexity, and maintains high device performance by enabling customized SiGe profiles for both NPN and PNP devices, making high-volume production more economically feasible.
Implementation Method 1
using a masking layer to define emitter regions for both NPN and PNP devices
Implementation Method 2
simultaneous implantation of dopants
Data Source
AI summary
A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and an NPN bipolar device in the bipolar region. The NPN bipolar device has an extrinsic base being self-aligned with an emitter of the NPN bipolar device. The extrinsic base of the NPN bipolar device and an emitter of the PNP bipolar device share a P type dopant.