Bipolar CMOS Select Device for Resistive Memory
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Solution Overview
Problem
Resistive sense memory technologies face challenges such as high current requirements for writing, which result in large area needs for MOSFET select transistors, limiting their integration and scalability in nonvolatile solid-state data storage devices.
Innovation Solution
A bipolar select device with a CMOS bipolar select transistor that has high drive current capability while consuming a small area, sharing one contact across multiple memory cells, and utilizing silicon on insulator technology to transform MOSFETs into lateral bipolar transistors for efficient current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If MOSFET select transistors are used to achieve the currents needed for writing, then the writing current requirement is met, but the area required becomes large
Solution Approach 1:
The patent transforms the MOSFET into a lateral bipolar transistor by changing the device structure and operating parameters. This parameter change enables the select transistor to achieve high drive current capability with significantly reduced area, directly resolving the contradiction between writing current requirement and transistor area.
Solution Approach 2:
The patent replaces the conventional MOSFET mechanism with a bipolar transistor mechanism that utilizes minority carrier injection and transport. This substitution fundamentally changes the current conduction mechanism, enabling higher current density in a smaller area, thus resolving the area-current contradiction.
2Area of stationary object
If the area of select transistors is reduced, then the memory array density increases, but the drive current capability decreases
Solution Approach 1:
By transforming the MOSFET into a lateral bipolar transistor, the patent changes the device physics to enable high current density in a compact footprint. The bipolar mechanism provides superior current gain and density, allowing reduced transistor area while maintaining or enhancing drive current capability.
Solution Approach 2:
The patent employs a composite structure combining silicon-on-insulator technology with lateral bipolar transistor design. This composite approach integrates multiple material and structural features to achieve both small area and high drive current capability simultaneously.
3Productivity
If more select transistors are used to increase memory array density, then the coverage increases, but the total area consumed increases
Solution Approach 1:
The transformation to lateral bipolar transistors reduces the area per select device, enabling higher memory array density within the same total area. This parameter change in device architecture directly improves productivity by increasing the number of memory cells that can be packed into a given area.
Solution Approach 2:
The patent shares one contact across multiple memory cells, implementing a segmented approach where a single select transistor can control access to multiple memory cell columns. This segmentation reduces the total number of select transistors needed, thereby reducing the total area consumed while maintaining high memory array density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables higher current flow per area, reducing the required area for resistive sense memory apparatus and increasing memory array density, addressing the limitations of conventional semiconductor transistor select devices.
Implementation Method 1
A bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact.
Data Source
AI summary
A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.