BiCMOS Collector Insulation Doping for High-Frequency Performance
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Solution Overview
Problem
Current complementary bipolar semiconductor devices face challenges in integrating both npn and pnp transistors with high-speed properties in CMOS technology, due to issues like high parasitic capacitance, complex process steps, and heat dissipation problems, which hinder the improvement of pnp-transistor performance and complicate CMOS integration.
Innovation Solution
A complementary bipolar semiconductor device with shallow field insulation regions and insulation doping between the collector region and substrate, allowing for lateral and vertical insulation, reducing parasitic capacitance and collector resistance, and enabling the integration of both transistor types in a CMOS process without the need for epitaxially buried collector layers or deep trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deep trenches and epitaxially buried collector layers are used for insulation, then vertical insulation is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The invention extracts and eliminates the need for deep trenches and epitaxially buried collector layers by utilizing the substrate's own doping structure for vertical insulation. The collector region is directly formed in the substrate without requiring additional insulation structures, thereby simplifying the device architecture while maintaining effective vertical insulation between collector and substrate.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support, electrical doping regions for transistor operation, and vertical insulation through its intrinsic doping structure. The collector region is directly formed in the substrate, making the substrate universally functional for both structural and electrical insulation purposes, eliminating the need for separate deep trench structures.
2Ease of manufacture
If shallow field insulation regions are used for lateral insulation, then manufacturing is simplified, but parasitic capacitance between collector and substrate increases
Solution Approach 1:
The invention applies local quality by creating a highly doped collector region with specific doping concentration and depth parameters optimized to minimize parasitic capacitance. The collector region is formed with precise local doping characteristics that reduce capacitance to the substrate while maintaining effective lateral insulation through the shallow field insulation regions.
Solution Approach 2:
The invention changes critical parameters including doping concentration, collector region depth, and field insulation depth to optimize the balance between parasitic capacitance reduction and lateral insulation effectiveness. By adjusting these parameters, the device achieves low parasitic capacitance while maintaining manufacturability through shallow field insulation structures.
3Adaptability or versatility
If both npn and pnp transistors are integrated in CMOS process, then circuit functionality is improved, but heat dissipation becomes problematic
Solution Approach 1:
The invention segments the substrate into distinct doped regions for npn and pnp transistors, with each transistor type having its own optimized doping profile and collector region characteristics. This segmentation allows independent thermal management and doping optimization for each transistor type, enabling effective heat dissipation while maintaining full complementary circuit functionality.
Solution Approach 2:
The invention changes doping parameters and collector region dimensions to optimize thermal properties. By adjusting doping concentrations and collector depths specifically for each transistor type, the device achieves improved heat dissipation characteristics while maintaining the ability to integrate both npn and pnp transistors for full complementary circuit operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the integration of both bipolar transistor types with improved high-frequency properties, reduces thermal stress, and allows for the production of low-defect, highly doped collector regions, achieving significant improvements in high-speed parameters, with npn-transistors reaching fT/fmax values of 180 GHz/185 GHz and pnp-transistors reaching 80 GHz/120 GHz, a two-fold improvement over the state of the art.
Implementation Method 1
an insulation doping region (116) which provides electrical insulation of the collector (111) and the substrate (1)
Implementation Method 2
a number of active regions which are provided thereon and which are delimited in the lateral direction by shallow field insulation regions
Implementation Method 3
vertical npn-bipolar transistors with an epitaxial base are arranged in a first subnumber of the active regions
Data Source
AI summary
A complementary BiCMOS semiconductor device comprises a substrate of a first conductivity type and a number of active regions which are provided therein and which are delimited in the lateral direction by shallow field insulation regions, in which vertical npn-bipolar transistors with an epitaxial base are arranged in a first subnumber of the active regions and vertical pnp-bipolar transistors with an epitaxial base are arranged in a second subnumber of the active regions, wherein either one transistor type or both transistor types have both a collector region and also a collector contact region in one and the same respective active region. To improve the high-frequency properties exclusively in a first transistor type in which the conductivity type of the substrate is identical to that of the collector region, an insulation doping region is provided between the collector region and the substrate.