Bipolar FET Epitaxial Layer Segmentation for Channel Isolation

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Solution Overview

Problem

Conventional approaches to integrating bipolar transistors with enhancement-mode (E-mode) and depletion-mode (D-mode) FETs on a substrate result in shared epitaxial layers, leading to undesirable coupling and performance interference between the E-mode and D-mode FETs, making it impossible to optimize one without affecting the other.

Innovation Solution

The solution involves forming separate epitaxial layers for each FET, with the E-mode FET's channel situated above and isolated from the D-mode FET's channel, allowing independent optimization of each transistor by physically and electrically decoupling them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If shared epitaxial layers are used to integrate bipolar transistors with E-mode and D-mode FETs, then device integration is achieved, but coupling occurs between the FETs affecting their respective performances

Engineering Contradiction:
Improvedevice integrationVSAvoidFET performance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent divides the epitaxial structure into separate layers: a first epitaxial layer containing the E-mode FET channel and a second epitaxial layer containing the D-mode FET channel. This segmentation prevents coupling between the FETs while maintaining integration on the same substrate, resolving the contradiction between integration and performance isolation.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If E-mode and D-mode FETs are integrated under the sub-collector of an HBT, then circuit design flexibility is increased, but the performance of one FET cannot be optimized without affecting the other

Engineering Contradiction:
Improvecircuit design flexibilityVSAvoidFET performance optimization
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent segments the FET channels into separate epitaxial layers, allowing independent optimization of E-mode and D-mode FET parameters without mutual interference, while still achieving integrated circuit design flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent resolves the optimization conflict by transitioning to a vertical stacking arrangement where E-mode and D-mode FETs occupy different vertical dimensions (separate epitaxial layers), enabling independent performance optimization while maintaining horizontal integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8901611B2Bipolar field effect transistor structures and methods of forming the same
Publication Date: 2014.12.02 SKYWORKS SOLUTIONS INC
  • US8901611B2 patent drawing
  • US8901611B2 patent drawing
  • US8901611B2 patent drawing

AI summary

Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET.