Bipolar Junction Transistor Coupled to Memory Cell String
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Solution Overview
Problem
As memory cell density increases in memory devices, controlling operations becomes challenging due to the complexity of accessing and managing large numbers of memory cells efficiently, particularly in multi-level cell structures where storing multiple bits per cell complicates read, programming, and erase operations.
Innovation Solution
The use of NPN and PNP bipolar junction transistors in memory devices allows for precise control of memory cell strings through various voltage signals, enabling efficient read, programming, and erase operations by selectively coupling memory cells to conductive lines, thereby managing the storage and retrieval of multiple bits per cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to improve storage capacity, then the number of memory cells per device area increases, but the complexity of controlling operations (read, programming, erase) increases
Solution Approach 1:
The memory array is divided into multiple independently controllable blocks, where each block contains a subset of memory cells that can be accessed separately. This segmentation allows the control logic to manage smaller groups of cells simultaneously, reducing the overall control complexity while maintaining high density through parallel block operations.
Solution Approach 2:
The patent introduces a block selection dimension in addition to the traditional row and column selection. By adding this hierarchical level of organization (block → row/column → cell), the control system can efficiently manage large numbers of cells by first selecting a subset of blocks, then operating within those selected blocks, thereby reducing the complexity of direct cell addressing.
2Quantity of substance
If multi-level cell structures are used to store multiple bits per cell, then storage capacity increases, but the complexity of read, programming, and erase operations increases
Solution Approach 1:
The multi-level cell structure is segmented into distinct programming and verification stages. Each programming operation targets specific threshold voltage ranges corresponding to different data states, and verification operations check these states independently. This segmentation of the programming and verification processes simplifies the control logic for handling multiple bits per cell.
Solution Approach 2:
The programming operation uses periodic voltage pulses applied to control gates to incrementally adjust threshold voltages of memory cells. By applying a sequence of programmed voltage pulses with specific timing and duration, the system can reliably program multiple bits per cell through controlled threshold voltage shifts, making the complex multi-level programming process manageable through repetitive, standardized pulse sequences.
Data Source
AI summary
Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.