3D Bipolar Memory Architecture Vertical Layering
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Solution Overview
Problem
Current memory devices face challenges with significant wiring overhead due to pitch mismatches, leading to reduced space for memory cell arrays on semiconductor wafers, which affects memory cell density and reliability.
Innovation Solution
The solution involves fabricating memory cells and drive circuits on different layers of a semiconductor wafer, with a two-terminal bi-directional access device in each memory cell, allowing for vertical alignment of drive circuits beneath the memory arrays, thereby optimizing space utilization and reducing wiring overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If peripheral circuitry is placed on the same layer as memory cell arrays, then drive circuits can be easily connected to memory cells, but the area overhead increases significantly, reducing space for memory cell arrays
Solution Approach 1:
The patent moves drive circuits from the same layer as memory cell arrays to a separate lower layer, utilizing the vertical dimension for circuit placement. This layer separation allows drive circuits to be positioned beneath memory cell arrays, reducing planar area overhead while maintaining electrical connections through vertical vias.
2Quantity of substance
If multiple wafers are used to increase memory cell density, then more memory cells can be fabricated, but wiring overhead due to pitch mismatches increases significantly
Solution Approach 1:
The patent integrates multiple memory cell arrays and their corresponding drive circuits onto a single wafer by utilizing vertical layering. This consolidation eliminates the need for multiple separate wafers and reduces wiring complexity by providing direct vertical connections between drive circuits and memory cells through aligned vias, avoiding pitch mismatch issues.
3Area of stationary object
If drive circuits are placed vertically below memory arrays, then area overhead is minimized and memory cell density increases, but alignment precision between layers must be maintained
Solution Approach 1:
The patent incorporates alignment features and registration marks during the fabrication process to ensure precise vertical alignment between the memory cell arrays on the upper layer and drive circuits on the lower layer. This preliminary alignment setup during manufacturing ensures that vertical connections are accurately formed without requiring excessive post-processing adjustment.
Data Source
AI summary
Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.