Bipolar-MOS Memory Circuit Reducing Manufacturing Complexity

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Solution Overview

Problem

Existing logic circuits, particularly those using CMOS and bipolar technologies, face challenges in reducing manufacturing costs and processing steps due to the need for multiple transistor types, which increases complexity and expense.

Innovation Solution

A circuit design that combines bipolar and single-type MOS logic, where bipolar transistors are manufactured in parallel with memory cell non-linear conductive elements, reducing the number of processing steps and masks required, thereby lowering costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If multiple transistor types (NMOS and PMOS) are used in CMOS circuits, then power consumption is reduced, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvepower consumptionVSAvoidmanufacturing complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges bipolar transistor technology with single-type MOS logic to create a hybrid circuit that achieves low power consumption without requiring both NMOS and PMOS transistors. The bipolar transistors provide efficient current switching while the single-type MOS transistors handle logic functions, eliminating the need for complex dual-type MOS manufacturing processes including multiple photolithography masks.

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If bipolar transistors are used for fast operation, then speed is improved, but power consumption increases

Engineering Contradiction:
Improveoperating speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent applies local quality by using bipolar transistors specifically for current switching functions where high speed is critical, while using single-type MOS transistors for logic functions where continuous current flow is avoided. This localized application of bipolar technology provides speed improvements in critical paths without incurring the continuous power consumption penalty of full bipolar logic circuits.

Inventive Principle:
Principle #3Local quality

3Device complexity

If single-type MOS logic is used, then manufacturing complexity is reduced, but operating speed decreases

Engineering Contradiction:
Improvemanufacturing complexityVSAvoidoperating speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent combines single-type MOS logic with bipolar transistors to create a hybrid architecture that maintains the manufacturing simplicity of single-type MOS circuits while incorporating bipolar transistors in strategic locations to provide fast switching and improve overall operating speed without requiring complex dual-type MOS manufacturing.

Inventive Principle:
Principle #5Merging (Combining)

4Adaptability or versatility

If multiple transistor types are manufactured, then circuit functionality is improved, but processing steps and masks increase

Engineering Contradiction:
Improvecircuit functionalityVSAvoidprocessing steps
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent merges the functionality of multiple transistor types into a hybrid circuit using bipolar transistors and single-type MOS transistors, achieving versatile circuit functionality without requiring the complex manufacturing processes needed for dual-type MOS circuits. The bipolar transistors can be manufactured using standard bipolar processes while the MOS transistors use simpler single-type processes, reducing overall manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9270269B2Bipolar-MOS memory circuit
Publication Date: 2016.02.23 WESTERN DIGITAL TECHNOLOGIES INC
  • US9270269B2 patent drawing
  • US9270269B2 patent drawing
  • US9270269B2 patent drawing

AI summary

Electronic memory circuits, and more particularly, low power electronic memory circuits having low manufacturing costs are disclosed. The present invention is a circuit design that utilizes two transistor types—bipolar and MOS (but, not both NMOS and PMOS) one of which can be manufactured together with the memory cell's non-linear conductive elements (such as a diode) thereby reducing the number of processing steps and masks and resulting in lower cost.