BiCMOS MTP Memory With Deep Trench Isolation Control Gate
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Solution Overview
Problem
Conventional multiple times programmable (MTP) memory circuits face challenges in achieving high retention, flexibility, and reduced manufacturing costs, particularly when integrated with BiCMOS processing, which often requires additional processing steps and compromises on other design goals like storage capacity and power consumption.
Innovation Solution
The implementation of a deep trench isolation (DTI) isolated control gate structure in MTP cells, using a combination of CMOS and bipolar processing steps, enhances breakdown voltage, allows for more flexible floating gate design, and reduces charge leakage, thereby improving retention time and data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional EEPROM processing steps are used in BiCMOS integration, then storage capacity is improved, but manufacturing cost increases due to numerous extra processing steps
Solution Approach 1:
The patent applies universality by designing MTP cell structures that can be fabricated using the same BiCMOS processing steps used for other circuit components on the chip. The deep trench isolation structure and control gate formation are integrated into the standard BiCMOS fabrication sequence, allowing memory and logic circuits to share common processing steps, thereby reducing manufacturing cost while maintaining storage capacity
Solution Approach 2:
The patent merges the MTP cell structure with standard BiCMOS processing by combining the control gate formation with the bipolar device fabrication steps. The deep trench isolation structure is formed using the same oxidation and etching steps used for bipolar transistor isolation, eliminating the need for separate memory-specific processing steps and reducing overall manufacturing complexity
2Adaptability or versatility
If control gate breakdown voltage is increased, then programming flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent achieves higher control gate breakdown voltage by changing the physical parameters of the control gate structure, specifically increasing the gate oxide thickness and adjusting the doping concentration in the control gate region. These parameter changes allow for higher programming voltages and improved programming flexibility without requiring fundamentally new manufacturing processes, thus avoiding increased manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high retention and increased flexibility in programming voltage and time, leading to improved data retention at higher temperatures and higher number of read cycles, while minimizing additional processing steps and maintaining compatibility with conventional BiCMOS processes.
Implementation Method 1
provides better breakdown voltage for diffused control gates
Implementation Method 2
provides for higher charge storage
Implementation Method 3
a deep trench isolation (DTI) isolated control gate formed of a first surface well implant above a first buried well implant
Implementation Method 4
provides for higher charge storage
Implementation Method 5
semiconductor system forming, on a common substrate, CMOS devices and bipolar devices
Data Source
AI summary
A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the buried carrier layer portion within the DTI trench. A floating gate is disposed on the carrier well. Optionally, a high voltage control gate is formed of a stack of the buried well implant and the surface well implant within the DTI trench. Optionally, a poly layer formed of a bipolar process base poly layer is disposed on the floating gate. Optionally, a shallow well isolation region is formed on the substrate, a floating gate is disposed on the shallow well region, and an overlaying control gate, formed of a bipolar process base poly, is disposed above the floating gate.