Positive-Negative Sampling Hold Circuit Without Inverter Pulse Overlap
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Solution Overview
Problem
Traditional sampling and holding (S/H) circuits for touch panels operate inefficiently, wasting 50% of clock cycles and experiencing pulse overlap due to transmission time delays in inverters, leading to asynchronous output of positive/negative sampling results, especially in high-speed and high-frequency applications.
Innovation Solution
A positive/negative S/H circuit that uses two capacitors and multiple charge and discharge switches to simultaneously sample and output signals, ensuring synchronous operation by controlling sampling and output times through switch control signals, thereby eliminating the need for inverters and reducing pulse overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If inverters are used to enable S/H circuits to operate on both positive and negative clock cycles, then the circuit can utilize 100% of clock cycles, but transmission time delay causes pulse overlap and operational disorder
Solution Approach 1:
The circuit is divided into two separate S/H circuits operating on different clock phases: one processes positive clock cycles while the other processes negative clock cycles. Each circuit has its own capacitor (first capacitor C1, second capacitor C2) and associated switches, eliminating the need for inverters and avoiding pulse overlap while maintaining 100% clock cycle utilization.
Solution Approach 2:
Instead of using inverters to convert negative pulses to positive pulses (which causes delay), the invention uses the negative clock cycles directly by designing a parallel S/H circuit that natively processes negative polarity signals. This inverts the conventional approach of converting all signals to one polarity.
2Adaptability or versatility
If inverters are used to perform direct phase conversion on sampled results, then positive/negative S/H results can be outputted, but transmission time delay prolongs signal waiting times
Solution Approach 1:
The circuit performs preliminary separation of positive and negative sampling operations during the sampling phase itself. The first capacitor samples during positive clock cycles while the second capacitor samples during negative clock cycles, so that both positive and negative S/H results are already prepared and ready for simultaneous output without requiring time-consuming inverter conversion later.
Solution Approach 2:
Both capacitors continuously sample and hold their respective signals simultaneously during their designated clock phases, maintaining continuous useful action. The first capacitor holds its signal ready for output while the second capacitor simultaneously holds its signal, eliminating waiting times that would occur if one signal had to be converted after sampling.
3Ease of operation
If traditional S/H circuits operate on only positive or negative clock cycles, then operational simplicity is maintained, but 50% of clock cycle is wasted
Solution Approach 1:
The circuit system achieves multi-functionality by having two S/H circuits work in parallel: one dedicated to positive clock cycles and another dedicated to negative clock cycles. Each circuit maintains operational simplicity with its own straightforward sampling and holding mechanism, while the combined system utilizes 100% of clock cycles, achieving both simplicity and high productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for efficient simultaneous sampling and output of positive/negative signals with the same magnitude but opposite polarities, improving operational synchronicity and reducing signal waiting times in high-speed S/H circuits.
Implementation Method 1
a first capacitor; a second capacitor connected in parallel with the operational amplifier forming an integration circuit
Implementation Method 2
a plurality of discharge switches correspondingly connected to discharge paths of the respective first and second capacitors for controlling the first and second capacitors to simultaneously output a respective first sampling signal and a second sampling signal
Data Source
AI summary
A positive/negative sampling and holding (S/H) circuit is disclosed herein. The positive/negative S/H circuit includes an operational amplifier, a first capacitor, a second capacitor being parallel with the first capacitor and forming an integration circuit with the operational amplifier, and several discharge switches correspondingly connecting discharge paths of the first and the second capacitors to control the first and the second capacitors to output a first sampling signal and a second sampling signal respectively, and herein, the first and the second sampling signals has the same magnitude but opposite voltage polarities.