Bipolar Selector Layout for Sneak-Path-Resistant Memory Arrays
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Solution Overview
Problem
High-density memory arrays face the sneak path problem due to cross-talk interference between adjacent memory cells, which is exacerbated by inefficient BEOL-fabricated selector devices that obstruct interconnect density and have high leakage and low mobility.
Innovation Solution
Fabricating selector devices in the substrate front-side using high-quality semiconductor layers and placing memory elements on the back-side to enable higher interconnect density and bandwidth, with each selector device comprising an NPN or PNP bipolar transistor or diode, allowing for efficient connections to a logic chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selector devices are inserted on top of each memory element in the BEOL, then the sneak path problem is mitigated, but the interconnect density is reduced and the BEOL area is fully occupied
Solution Approach 1:
The patent transitions from a planar BEOL architecture to a 3D stacked architecture where selector devices are placed in the vertical dimension above memory elements. This dimensional change allows selector devices to protect memory cells without occupying horizontal interconnect space, resolving the contradiction between sneak path mitigation and interconnect density.
Solution Approach 2:
The patent implements a nested structure where selector devices are positioned above and integrated with memory elements in a stacked configuration. The selector devices effectively 'contain' or 'protect' the memory elements from sneak paths while allowing interconnects to pass through or around the structure, maintaining high interconnect density.
2Ease of manufacture
If amorphous and poly-crystalline materials are used in the BEOL for selector devices, then fabrication is enabled, but leakage is high and mobility is low due to material defects
Solution Approach 1:
The patent employs composite material structures in the stacked selector device architecture, combining different semiconductor material layers (including crystalline and amorphous/poly-crystalline materials) to achieve both manufacturability and improved electrical performance. The composite structure allows optimization of each layer's properties to reduce defects while maintaining fabrication feasibility.
Solution Approach 2:
The patent changes material parameters by transitioning from single-phase amorphous/poly-crystalline materials to multi-layer composite structures with controlled crystallinity. This parameter change enables better control over defect density, leakage, and mobility while preserving the ease of manufacture through established semiconductor fabrication processes.
3Reliability
If selector devices are placed in the BEOL, then memory cell protection is achieved, but the processing temperature and complexity increase
Solution Approach 1:
The patent implements preliminary action by forming selector devices in a separate FEOL process before bonding to the memory array substrate. This allows selector devices to be fabricated at lower temperatures in the FEOL, and then integrated with the memory array through bonding, avoiding the need to process selector devices at high temperatures in the BEOL.
Solution Approach 2:
The patent segments the fabrication process into two independent parts: FEOL processing for selector devices and BEOL processing for memory elements, followed by bonding. This segmentation allows each part to be optimized for its specific thermal requirements, reducing the overall thermal budget and complexity compared to integrated BEOL processing.
Data Source
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AI summary
The present disclosure is related to the field of memory devices including memory arrays, in particular magnetic memory devices. The invention provides a method for fabricating a memory device, and the memory device. The method comprises: processing a plurality of selector devices (11) in a semiconductor layer (12) of a first substrate, processing an interconnect layer (14) on a front-side of the semiconductor layer, the interconnect layer comprising an interconnect structure (15) electrically connected to the plurality of selector devices, processing a plurality of memory elements (16) in an oxide layer (17) of the first substrate arranged on a back-side of the semiconductor layer, each memory element being electrically connected to one of the selector devices, and processing one or more vias (18) through the semiconductor layer to electrically connect the memory elements to the interconnect structure.