High Speed and High Voltage Bipolar Transistor Integration
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Solution Overview
Problem
Conventional methods for integrating high speed and high voltage bipolar transistors on a semiconductor substrate are limited by the thickness of the epitaxial collector layer, which restricts the collector-to-emitter breakdown voltage (BVCEO) of high voltage transistors to less than 5.0 volts, increasing manufacturing costs due to the need for separate epitaxial collector layers.
Innovation Solution
A method involving a high energy implant region formed below the epitaxial layer replaces the conventional buried subcollector, allowing for the integration of high speed bipolar transistors with a cutoff frequency of 200.0 MHz or greater and high voltage bipolar transistors with a BVCEO greater than 5.0 volts on the same substrate without additional masking layers, reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a thin epitaxial collector layer is used to achieve high speed transistor performance (FT ≥ 200.0 MHz), then the collector transit time and collector resistance are reduced, but the collector-to-emitter breakdown voltage (BVCEO) of high voltage bipolar transistors is limited to between 3.0 volts and 4.0 volts
Solution Approach 1:
The patent divides the semiconductor substrate into distinct high speed transistor regions and high voltage transistor regions. Each region is independently processed with appropriate epitaxial layer thicknesses - thin layers in high speed regions for high frequency performance, and thick layers in high voltage regions for high breakdown voltage. This spatial segmentation allows both transistor types to coexist on the same die without performance compromise.
Solution Approach 2:
The patent applies different epitaxial layer thicknesses to different locations on the semiconductor substrate based on the specific requirements of each transistor region. High speed transistor regions receive thin epitaxial layers (e.g., 0.5-2.0 micrometers) optimized for fast switching, while high voltage transistor regions receive thick epitaxial layers (e.g., 5.0-15.0 micrometers) optimized for high breakdown voltage. This local optimization resolves the contradiction between speed and voltage requirements.
2Adaptability or versatility
If separate epitaxial collector layers with different thicknesses are grown to integrate high voltage and high speed bipolar transistors, then both transistor types can be fabricated with optimal performance, but manufacturing cost significantly increases
Solution Approach 1:
The patent combines multiple transistor types (high speed and high voltage bipolar transistors) into a single integrated circuit fabricated on one semiconductor die using a unified fabrication process. By using selective region processing and standard epitaxial growth techniques that can accommodate varying layer thicknesses across different die regions, the patent achieves integration without requiring separate manufacturing lines or additional costly process steps.
Solution Approach 2:
The patent develops a universal fabrication process that can simultaneously produce both high speed and high voltage bipolar transistors on the same semiconductor substrate. The process uses a single epitaxial growth step that can create regions of different thicknesses, along with standardized doping and fabrication techniques applicable to both transistor types, thereby reducing manufacturing complexity and cost compared to separate fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of high speed and high voltage bipolar transistors with improved performance, achieving a BVCEO greater than 5.0 volts and maintaining high speed capabilities while reducing manufacturing costs by eliminating the need for additional masking layers and separate epitaxial collector layers.
Implementation Method 1
A method is provided involving a high energy implant region formed below an epitaxial layer
Data Source
AI summary
According to an exemplary embodiment, a method for integrating a high speed bipolar transistor in a high speed transistor region of a substrate with a high voltage transistor in a high voltage transistor region of the substrate includes forming a buried subcollector in the high speed transistor region of the substrate. The method further includes forming a first high energy implant region in the high voltage transistor region of the substrate, where the first high energy implant region extends to a depth greater than a depth of a peak dopant concentration of the buried subcollector, thereby increasing a collector-to-emitter breakdown voltage of the high voltage transistor. The collector-to-emitter breakdown voltage of the high voltage transistor can be greater than approximately 5.0 volts. The high speed bipolar transistor can have a cutoff frequency of greater approximately 200.0 GHz.