Bipolar Transistor Cavity Etching for Planar Contact Formation
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Solution Overview
Problem
Bipolar transistor manufacturing methods face challenges with the etching of thick stacks of layers, which can result in non-planar layers, causing issues during contact formation.
Innovation Solution
A method involving the formation of a first stack of layers on a substrate, followed by etching a cavity that reaches the substrate without removing layers covering the base material, allowing for the epitaxial growth of collector and base portions within the cavity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If thick stacks of layers are etched during emitter formation, then the cavity can reach the substrate, but non-planar layers are formed causing problems during contact formation
Solution Approach 1:
The patent applies preliminary action by forming a planarizing layer of insulating material over the etched stack before depositing the emitter. This planarizing layer is formed in advance to compensate for the non-planarity created by etching through thick stacks, thereby preventing contact formation problems while maintaining the required cavity depth to reach the substrate.
2Length of stationary object
If layers covering the base material are removed during etching, then the cavity can be formed, but the base material becomes exposed and vulnerable
Solution Approach 1:
The patent uses an intermediary approach by selectively removing only the third insulating layer during etching, while preserving the first and second insulating layers that cover the base material. This selective etching allows the cavity to reach the substrate while the remaining insulating layers continue to protect the base material, thus maintaining reliability.
3Length of moving object
If critical dimensions are reduced below 200 nm, then transistor performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the manufacturing process into distinct, well-defined steps: forming the first stack with multiple insulating layers, selectively etching only the third layer, forming the planarizing layer, and depositing the emitter. This segmentation of the manufacturing process into manageable stages reduces overall complexity while enabling precise control of critical dimensions below 200 nm.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of planar surfaces, facilitating easier contact formation and allowing for the creation of bipolar transistors with critical dimensions less than 200 nm.
Implementation Method 1
the first and second portions are formed by epitaxial growth
Data Source
AI summary
To manufacture a bipolar transistor, a first stack of layers including a first layer made of the material of the base of the bipolar transistor is formed between second and third insulating layers. A first cavity is then formed crossing the first stack in such a way as to reach the substrate. The forming of the first cavity includes an etching of no layer covering the first layer other than the third layer. A first portion of the collector of the bipolar transistor and a second portion of the base of the bipolar transistor are then formed in the first cavity.