Self-Aligned Bipolar Transistor Cavity Geometry for Boron Diffusion
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Solution Overview
Problem
Prior art methods for manufacturing fully self-aligned bipolar transistors often result in incomplete connections between polysilicon and monocrystalline silicon surfaces and insufficient boron diffusion into the base-collector corner, leading to increased base resistance and base-collector current.
Innovation Solution
A modified cavity formation using multiple layers of silicon oxide with different wet etch rates to create a 'stair step' geometry, optimizing selective epitaxial growth and enhancing boron diffusion through the formation of polysilicon rich corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a standard cavity formation method is used, then the manufacturing process is simple, but the connection between polysilicon and monocrystalline silicon surfaces is incomplete and boron diffusion is insufficient
Solution Approach 1:
The cavity formation process is segmented into multiple stages using different oxide layers (first oxide layer, second oxide layer, third oxide layer) with different etch rates. Each layer serves a specific function in creating the final cavity geometry, allowing precise control over the connection interface between polysilicon and monocrystalline silicon while maintaining a manageable process structure
Solution Approach 2:
Different regions of the cavity are given different geometries through the selective removal of oxide layers. The 'stair step' configuration creates localized variations in cavity depth and shape, optimizing the connection area between materials while maintaining overall process simplicity through the use of standard deposition and etching techniques
2Manufacturing precision
If a standard cavity geometry is used, then the etch process is simple, but boron diffusion into the base-collector corner is insufficient
Solution Approach 1:
The cavity is pre-formed with a 'stair step' geometry using multiple oxide layers before the selective epitaxial growth and boron diffusion processes. This preliminary geometric configuration ensures that boron can efficiently diffuse into the base-collector corner during subsequent processing, as the pre-configured steps provide optimal pathways for dopant diffusion without requiring complex in-situ geometry modification
Solution Approach 2:
The cavity geometry is extended into the vertical dimension with multiple 'stair step' levels created by selective removal of oxide layers at different heights. This multi-level vertical structure increases the surface area and creates multiple diffusion pathways for boron, enhancing diffusion efficiency without complicating the horizontal planar process steps
3Productivity
If oxide layers with different etch rates are used, then selective epitaxial growth is optimized, but the process steps increase
Solution Approach 1:
The process utilizes oxide layers with different etch rate parameters (first oxide layer, second oxide layer, third oxide layer) to enable selective removal during cavity formation. This parameter variation allows the epitaxial growth process to be optimized for selectivity and control, while the underlying deposition and etching techniques remain standard industrial processes, balancing productivity improvement with process complexity management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a contiguous connection between polysilicon and monocrystalline silicon, reduces base-collector capacitance, and increases boron diffusion rates, improving the overall performance of bipolar transistors.
Implementation Method 1
A modified cavity formation using multiple layers of silicon oxide with different wet etch rates to create a 'stair step' geometry
Implementation Method 2
Then a diluted hydrofluoric acid (HF) etch procedure is applied to etch laterally through the layer of silicon oxide 140 to form a cavity 180
Implementation Method 3
the selective epitaxial growth (SEG) of a base portion of the transistor
Implementation Method 4
insufficient boron diffusion from the highly doped polysilicon material of the raised external base into the base-collector corner
Data Source
AI summary
A system and method are disclosed for providing a fully self aligned bipolar transistor using modified cavity formation to optimize selective epitaxial growth. A collector of a transistor is formed and at least two layers of silicon oxide are formed above the collector and covered with a polysilicon external raised base. Then an emitter window is etched through the polysilicon external raised base down to the top layer of silicon oxide. A wet etch process is performed to form a cavity in the at least two layers of silicon oxide. Different wet etch rates of the silicon layers with respect to the wet etch process cause the cavity to be formed with a shape that optimizes selective epitaxial growth in the cavity. Polysilicon rich corners and a monocrystalline silicon base are then formed within the cavity.