Bipolar Transistor Emitter Pillar CMP Dishing Prevention
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Solution Overview
Problem
The challenge in manufacturing bipolar transistors with wide emitter areas is the dishing effect during chemical mechanical polishing (CMP), which removes excess emitter material from inside the base window, limiting the maximum dimensions of the emitter and affecting the reliability of current mirrors in RF applications.
Innovation Solution
Incorporating polishing-resistant pillars within the base window to prevent excessive dishing during CMP, allowing for increased emitter dimensions without additional process steps, and using a layer stack including insulating, conductive, and protection layers to facilitate this, along with epitaxial growth and sidewall spacers to enhance base formation and prevent boron impurity outdiffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the base window dimensions are increased to create wider emitter areas for handling large currents, then the current handling capability is improved, but the dishing effect during CMP becomes so pronounced that substantially all emitter material is removed from inside the base window
Solution Approach 1:
A polishing-resistant layer is introduced as an intermediary element within the base window structure. This layer acts as a mediator during the CMP process, protecting the underlying emitter material from excessive removal while allowing the polishing process to proceed normally on surrounding areas. The polishing-resistant layer is strategically positioned to prevent the dishing effect from consuming all emitter material in wide base windows.
Solution Approach 2:
The polishing-resistant layer is deposited in advance before the CMP process to counteract the harmful dishing effect. By establishing this protective layer beforehand, the patent prevents the excessive removal of emitter material that would otherwise occur during polishing of wide base windows, thereby maintaining emitter dimensions within acceptable tolerances.
2Shape
If chemical mechanical polishing is used to remove excess emitter material from outside the base window, then the planarization is improved, but the dishing effect removes emitter material from inside the base window as well
Solution Approach 1:
The polishing-resistant layer serves as a protective intermediary during the CMP process. It allows the polishing mechanism to achieve proper planarity of the emitter surface while simultaneously protecting the emitter material inside the base window from being completely removed. This intermediary layer enables the CMP process to fulfill its planarization function without compromising emitter integrity.
Solution Approach 2:
The polishing-resistant layer is selectively deposited only in specific regions where protection is needed, creating local variations in polishing resistance. This local quality approach allows different parts of the emitter structure to have different properties - areas with the polishing-resistant layer are protected from excessive removal while other areas can be properly planarized.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the routine production of bipolar transistors with base windows exceeding 2 μm in width, maintaining high-quality performance and minimizing detrimental effects on transistor performance, while being cost-effective for RF applications.
Implementation Method 1
growing an epitaxial layer in the base window
Implementation Method 2
forming said sidewall spacers on said epitaxial layer... to prevent boron impurity outdiffusion
Implementation Method 3
planarizing the deposited emitter material by polishing... using chemical mechanical polishing (CMP)
Data Source
AI summary
Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method.