Self-aligned Bipolar Transistor via In-situ Doped Emitter Plug
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Solution Overview
Problem
Existing bipolar transistor structures face challenges in achieving self-alignment and reducing emitter size due to limitations in using sacrificial emitters, which result in operational degradation and yield loss, especially as device dimensions decrease.
Innovation Solution
The use of a selective or non-selective in-situ doped emitter plug achieves self-alignment by eliminating the complexities of sacrificial emitters, allowing for a sloped emitter etch and reducing emitter width below lithographic capabilities, while also simplifying the extrinsic base implant process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sacrificial emitters are used to achieve self-alignment, then emitter alignment precision is improved, but device complexity and manufacturing yield deteriorate due to multiple deposition and etch steps leaving residues
Solution Approach 1:
The patent extracts and eliminates the sacrificial emitter layer from the fabrication process. Instead of depositing polysilicon sacrificial emitters that require multiple etch steps and leave residues, the invention uses a simplified process where the emitter is formed directly without sacrificial materials, thereby improving yield while maintaining alignment precision through self-aligned oxidation and etching steps
Solution Approach 2:
The oxide layer serves multiple functions: it acts as a mask for self-aligned emitter formation, provides lateral isolation between emitter and base, and enables precise dimension control. This multi-functional approach replaces the need for separate sacrificial emitter layers and multiple processing steps, simplifying the overall fabrication process
2Manufacturing precision
If inside spacers are used to define emitter dimension and provide lateral isolation, then emitter-base isolation is improved, but device size reduction becomes problematic as emitter window size decreases
Solution Approach 1:
The patent transitions from using lateral spacers (horizontal dimension) to using a sloped oxide mask (angular/vertical dimension) for defining emitter dimensions. The sloped oxide layer creates a self-aligned emitter window through angular etching, eliminating the need for inside spacers and enabling smaller emitter windows while maintaining adequate emitter-base isolation
3Manufacturing precision
If multiple polysilicon and dielectric layers are deposited and etched back for self-alignment, then self-aligned bipolar architecture is achieved, but residual materials remain causing operational degradation
Solution Approach 1:
The patent uses a disposable oxide mask layer that is selectively removed after serving its purpose. The oxide layer is deposited, patterned at an angle, and then completely removed after defining the emitter window, leaving no persistent residues. This approach achieves self-alignment without the operational degradation caused by residual polysilicon and dielectric materials from traditional multi-layer processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of bipolar transistors with narrower emitters and improved RF performance by eliminating residues and reducing emitter fringe capacitance, enhancing integration density and operational efficiency.
Implementation Method 1
selective growth of a doped monocrystalline/polycrystalline emitter in an oxide window
Data Source
AI summary
A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.