Bipolar Transistor Field Plate for High Voltage Speed Trade-off
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Solution Overview
Problem
The manufacturing of bipolar transistors with a field plate to create a RESURF effect in the depletion region is costly and challenging, especially in BiCMOS technology, as it requires precise control of doping levels to balance high-frequency and high-voltage performance, which is difficult to achieve without compromising the electric field and avalanche characteristics.
Innovation Solution
A method for manufacturing a bipolar transistor with a field plate electrically connected to the emitter, using a silicon nitride spacer to protect the base region from excessive doping diffusion, allowing for a cost-effective integration in CMOS technology, where the field plate is formed in a single etching step close to the base-collector junction, and a silicon oxide lining is used to prevent defects and enhance electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high collector doping level is used to increase peak current gain cut-off frequency fT, then fT is improved, but collector-emitter breakdown voltage BVCEO deteriorates
Solution Approach 1:
The patent applies different doping levels to different regions: high doping in the collector bulk to increase fT, and low doping in the depletion region to maintain BVCEO. The field plate structure creates a localized low-doping region that extends the depletion region without compromising the overall high-doping benefit for frequency performance.
Solution Approach 2:
The field plate acts as an intermediary structure that modifies the electric field distribution. It introduces a controlled potential that extends the depletion region into the collector, thereby reducing the maximum electric field strength and postponing avalanche breakdown while maintaining the high-frequency characteristics.
2Reliability
If low collector doping level is used to increase collector-emitter breakdown voltage BVCEO, then BVCEO is improved, but peak current gain cut-off frequency fT deteriorates
Solution Approach 1:
The patent creates a spatially varying doping profile where the collector has high bulk doping for frequency performance but a low-doped depletion region for voltage breakdown performance. This local differentiation allows simultaneous optimization of both contradictory parameters.
Solution Approach 2:
The field plate extends the depletion region in the vertical dimension into the collector bulk, creating a three-dimensional doping profile that resolves the contradiction. The depletion region depth becomes a controllable parameter that independently affects BVCEO without compromising the surface doping level that determines fT.
3Reliability
If field plate is applied to extend depletion region and reduce electric field, then collector-emitter breakdown voltage BVCEO is improved, but device complexity increases
Solution Approach 1:
The field plate structure serves multiple functions: it extends the depletion region to increase BVCEO, controls the electric field distribution to reduce maximum field strength, and can be integrated with existing CMOS process steps. This multi-functionality justifies the added structural complexity.
4Manufacturing precision
If silicon nitride spacer is used to protect base region from doping diffusion, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The silicon nitride spacer is deposited beforehand to establish a diffusion barrier before doping processes occur. This preliminary protective action prevents base doping contamination during subsequent manufacturing steps, ensuring precise doping profiles without requiring complex in-process monitoring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of bipolar transistors suitable for high-frequency and high-voltage applications, such as RF power amplifiers, by effectively extending the depletion region and reducing the electric field, thus overcoming the Johnson limit and improving the product of peak current gain cut-off frequency and collector-emitter breakdown voltage.
Implementation Method 1
using a silicon nitride spacer to protect the base region from excessive doping diffusion
Implementation Method 2
a bipolar transistor having a field plate to create a RESURF effect in the depletion region
Implementation Method 3
a silicon oxide lining is used to prevent defects and enhance electrical isolation
Data Source
Figure 1~2
Figure 3~4
Figure 5(a)~5(b)
AI summary
Disclosed is a method of manufacturing a bipolar transistor, the method comprising providing a semiconductor substrate (10) including a collector region(11); forming a base layer (30) on the semiconductor substrate; forming an etch protect layer (32, 34) on a portion of the base layer defining an emitter region; forming a base contact layer (35) over the etch protect layer and the base layer; forming an electrically insulating layer (60) over the base layer; etching an opening (70) in the resultant structure formed after the formation of the electrically insulating layer, said opening comprising an emitter window portion (72) exposing at least a part of the etch protect layer and a field plate trench portion (74) adjacent to the emitter window portion extending through the base layer, the base contact layer and into the collector region; lining said opening with an electrically insulating material (52, 54); exposing said emitter region; and filling the lined opening with an electrically conductive material. A bipolar transistor manufactured in accordance with this method and an IC including such a bipolar transistor are also disclosed.