Bipolar Transistor Memory Array Floating Body Design
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Solution Overview
Problem
1T-DRAM devices with high integration face challenges in maintaining good data retention characteristics due to small floating body areas, which compromises their ability to achieve both high integration and good data retention.
Innovation Solution
A 1T-DRAM device design featuring an active pattern with protrusions and a recess on an insulation layer, where the base region acts as a floating body, and impurity regions function as a bipolar transistor, allowing for improved data storage and retrieval through controlled voltage applications, with a gate electrode surrounding the active pattern to enhance gate capacitance and charge control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 1T-DRAM devices have a high degree of integration, then device density is improved, but data retention characteristics deteriorate due to small floating body area
Solution Approach 1:
The invention transitions from a planar floating body structure to a three-dimensional protruding structure. The active pattern forms vertical protrusions that extend upward from the substrate, creating a floating body with significant volume in the vertical dimension. This dimensional change allows the floating body to maintain adequate charge storage capacity even when the planar footprint is reduced for high-density integration.
Solution Approach 2:
The invention changes the geometric parameters of the floating body by forming protrusions with controlled height and cross-sectional area. By adjusting the protrusion dimensions, the floating body volume is optimized to provide sufficient charge storage for good data retention while occupying minimal planar space, thereby enabling high device integration density.
2Reliability
If the floating body area is increased to improve data retention, then device area is increased, but integration density deteriorates
Solution Approach 1:
The floating body is formed as a vertical protrusion rather than a planar region. This allows the charge storage volume to be increased by extending in the vertical dimension (height) while maintaining a small planar footprint. The protruding structure provides adequate floating body volume for data retention without consuming excessive device area.
Solution Approach 2:
The invention optimizes the geometric parameters of the floating body by controlling the protrusion height and cross-sectional dimensions. This parameter optimization enables the floating body to achieve sufficient volume for reliable data storage while minimizing the planar area occupied, thus maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves good electrical characteristics, including high integration, effective data retention, and refresh characteristics by increasing the volume of the floating body for charge storage, while maintaining a high gate capacitance and channel control.
Implementation Method 1
A gate electrode is on the gate insulation layer, the gate electrode surrounding a lower portion of the active pattern and partially filling the recess
Implementation Method 2
The first impurity region may serve as an emitter of the bipolar transistor. The second impurity region may serve as a collector of the bipolar transistor
Data Source
AI summary
A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the protrusions. The active pattern includes a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively, and a base region at the other portions serving as a floating body for storing data. The gate insulation layer is formed on a surface of the active pattern. The gate electrode is formed on the gate insulation layer, and surrounds a lower portion of the active pattern and partially fills the recess.