Bipolar Transistor Manufacturing Using Overhanging Insulator
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Solution Overview
Problem
The existing method for manufacturing semiconductor devices with bipolar transistors has a low yield, leading to increased costs due to the need for complex and costly process steps like CMP and separate insulating region formation.
Innovation Solution
The method involves forming a second insulating layer with an overhanging end portion to provide space for the polycrystalline vertical part of the further semiconductor layer, allowing for self-aligned processing and eliminating the need for CMP, using wet or dry etching to remove upper horizontal and vertical parts, and forming spacers below the overhanging portion for cost-effective and high-yield transistor production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP and separate insulating region formation are used, then manufacturing precision is improved, but device complexity and production cost increase
Solution Approach 1:
The patent extracts and eliminates the CMP step from the manufacturing process by designing a structure where the insulating layer naturally overhangs the semiconductor layer, providing self-planarization without requiring mechanical polishing. This removes a complex and costly process step while maintaining the necessary precision.
Solution Approach 2:
The insulating layer is formed with an overhanging configuration before the semiconductor layer is deposited. This preliminary structural arrangement ensures that subsequent etching steps automatically create the required planar surface and insulating regions without requiring additional CMP or separate insulating region formation steps.
2Manufacturing precision
If CMP is used to remove upper parts of insulating layer and semiconductor layer, then manufacturing precision is improved, but productivity decreases due to costly and time-consuming process
Solution Approach 1:
The patent replaces the mechanical CMP process with a chemical etching process. The overhanging insulating layer structure enables selective chemical etching that automatically achieves the required surface flatness and dimensional precision without mechanical polishing, thereby improving productivity and reducing costs.
Solution Approach 2:
The overhanging insulating layer structure serves multiple functions automatically: it provides the planarizing mask, defines the insulating region boundaries, and enables self-aligned etching. This self-service mechanism eliminates the need for separate CMP and insulating region formation steps, improving both precision and productivity.
3Manufacturing precision
If separate insulating region formation is used, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent merges the insulating layer formation and the insulating region definition into a single structural feature—the overhanging insulating layer. This unified structure simultaneously provides electrical isolation and defines the lateral boundaries of insulating regions, eliminating the need for separate formation steps while maintaining precise alignment.
Solution Approach 2:
The overhanging insulating layer performs multiple functions: it acts as a planarizing mask, defines insulating region boundaries, provides self-alignment for subsequent etching, and ensures proper electrical isolation. This multi-functional design simplifies the overall manufacturing process while maintaining high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with high-frequency behavior and reduced costs, achieving high yield and low production costs by simplifying the process and eliminating critical steps like CMP, while maintaining small lateral dimensions and good high-frequency properties.
Implementation Method 1
by non-selective epitaxial growth a further semiconductor layer is deposited of which a monocrystalline horizontal part on the bottom of the opening forms the base region and of which a polycrystalline vertical part on a side face of the opening is connected to the polycrystalline layer
Data Source
AI summary
The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one bipolar transistor having an emitter region (1), a base region (2) and a collector region (3), wherein in the semiconductor body (12) a first semiconductor region (13) is formed that forms one (3) of the collector and emitter regions (1,3) and on the surface of the semiconductor body (12) a stack of layers is formed comprising a first insulating layer (4), a polycrystalline semiconductor layer (5) and a second insulating layer (6) in which stack an opening (7) is formed, after which by non-selective epitaxial growth a further semiconductor layer (22) is deposited of which a monocrystalline horizontal part on the bottom of the opening (7) forms the base region (2) and of which a polycrystalline vertical part (2A) on a side face of the opening (7) is connected to the polycrystalline semiconductor layer (5), after which spacers (S) are formed parallel to the side face of the opening (7) and a second semiconductor region (31) is formed between said spacers (S) forming the other one (1) of the emitter and collector regions (1,3). According to the invention the above method is characterized in that before the further semiconductor layer (22) is deposited, the second insulating layer (6) is provided with an end portion (6A) that viewed in projection overhangs an end portion (5A) of the underlying semiconductor layer (5). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.