Bi-layer Dielectric Structure for Printed FETs
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Solution Overview
Problem
Low-k dielectric materials used in solution processed and printed FETs result in high operating voltages due to low capacitance, and perfluoropolymer dielectrics have low surface energy, making further processing difficult, especially with rough underlying layers and issues with pin-hole free film production.
Innovation Solution
A bi-layer dielectric structure is employed, comprising a low-k material as an interface layer and a high-k relaxor layer, with the addition of a solid surfactant to enhance surface energy for solution processing, allowing for a thicker high-k dielectric layer to reduce gate leakage and improve film formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a thin low-k dielectric layer is used to reduce operating voltage, then operating voltage is reduced, but gate leakage increases significantly
Solution Approach 1:
The patent employs a bi-layer dielectric structure combining low-k and high-k materials. The low-k layer (e.g., perfluoropolymer) provides the interface with the semiconductor, while the high-k layer (e.g., PVDF copolymer relaxor) is deposited on top to provide high capacitance. This composite structure enables achieving low operating voltages without the gate leakage problems associated with thin low-k layers alone.
2Reliability
If perfluoropolymer dielectric is used to prevent charge trapping and ensure solvent compatibility, then charge transport mobility is improved, but surface energy becomes too low for further solution processing
Solution Approach 1:
The bi-layer dielectric structure combines perfluoropolymer (low-k) with PVDF copolymer relaxor (high-k). The perfluoropolymer layer maintains its low surface energy properties for preventing charge trapping, while the PVDF copolymer layer provides higher surface energy that enables subsequent solution processing steps.
Solution Approach 2:
The patent modifies the surface energy parameter by introducing the PVDF copolymer relaxor layer with different surface properties. This layer has higher surface energy compared to the perfluoropolymer, thereby enabling further solution processing while the underlying perfluoropolymer layer maintains its charge transport benefits.
3Use of energy by moving object
If dielectric thickness is reduced to achieve desired operating voltage, then operating voltage decreases, but pin-hole free film production becomes difficult on rough underlying layers
Solution Approach 1:
The bi-layer structure allows the high-k PVDF copolymer relaxor layer to be deposited on top of the low-k layer, providing sufficient total thickness for pin-hole free film formation while maintaining the low operating voltage enabled by the high capacitance of the high-k material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bi-layer dielectric structure achieves low operating voltages, high areal capacitance, and low leakage currents, enabling efficient solution processing and improved performance in printed electronic devices, such as FETs and capacitors, while maintaining high charge transport mobility.
Implementation Method 1
The low dielectric constant (k) of these materials leads to low capacitance and therefore high operating voltages
Implementation Method 2
with the addition of a solid surfactant to enhance surface energy for solution processing
Data Source
AI summary
A device, including a substrate, an electronically active component on the substrate, an interface dielectric on the semiconductor, and a relaxor dielectric on the interface dielectric. The relaxor dielectric includes a surfactant that is solid at room temperature.